411     int pir = pnv_xive2_get_current_pir(xive);  in pnv_xive2_inject_notify()  local
412     int thread_nr = PNV10_PIR2THREAD(pir);  in pnv_xive2_inject_notify()
413     int thread_topo_id = PNV10_PIR2CHIP(pir);  in pnv_xive2_inject_notify()
618     int pir = ppc_cpu_pir(cpu);  in pnv_xive2_is_cpu_enabled()  local
619     uint32_t fc = PNV10_PIR2FUSEDCORE(pir);  in pnv_xive2_is_cpu_enabled()
621     uint32_t bit = pir & 0x3f;  in pnv_xive2_is_cpu_enabled()
708     int pir = ppc_cpu_pir(cpu);  in pnv_xive2_tm_get_xive()  local
713         xive2_error(xive, "IC: CPU %x is not enabled", pir);  in pnv_xive2_tm_get_xive()
2045 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir)  in pnv_xive2_get_indirect_tctx()  argument
2050     cpu = pnv_chip_find_cpu(chip, pir);  in pnv_xive2_get_indirect_tctx()
2052         xive2_error(xive, "IC: invalid PIR %x for indirect access", pir);  in pnv_xive2_get_indirect_tctx()
2057         xive2_error(xive, "IC: CPU %x is not enabled", pir);  in pnv_xive2_get_indirect_tctx()
2069     uint32_t pir;  in pnv_xive2_ic_tm_indirect_read()  local
2073     pir = pnv_xive2_ic_tm_get_pir(xive, offset);  in pnv_xive2_ic_tm_indirect_read()
2075     tctx = pnv_xive2_get_indirect_tctx(xive, pir);  in pnv_xive2_ic_tm_indirect_read()
2089     uint32_t pir;  in pnv_xive2_ic_tm_indirect_write()  local
2092     pir = pnv_xive2_ic_tm_get_pir(xive, offset);  in pnv_xive2_ic_tm_indirect_write()
2094     tctx = pnv_xive2_get_indirect_tctx(xive, pir);  in pnv_xive2_ic_tm_indirect_write()