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Searched refs:pin (Results 1 – 25 of 2135) sorted by relevance

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/openbmc/linux/drivers/media/cec/core/
H A Dcec-pin.c111 static void cec_pin_update(struct cec_pin *pin, bool v, bool force) in cec_pin_update() argument
113 if (!force && v == pin->adap->cec_pin_is_high) in cec_pin_update()
116 pin->adap->cec_pin_is_high = v; in cec_pin_update()
117 if (atomic_read(&pin->work_pin_num_events) < CEC_NUM_PIN_EVENTS) { in cec_pin_update()
120 if (pin->work_pin_events_dropped) { in cec_pin_update()
121 pin->work_pin_events_dropped = false; in cec_pin_update()
124 pin->work_pin_events[pin->work_pin_events_wr] = ev; in cec_pin_update()
125 pin->work_pin_ts[pin->work_pin_events_wr] = ktime_get(); in cec_pin_update()
126 pin->work_pin_events_wr = in cec_pin_update()
127 (pin->work_pin_events_wr + 1) % CEC_NUM_PIN_EVENTS; in cec_pin_update()
[all …]
/openbmc/u-boot/board/sunxi/
H A Dgmac.c11 int pin; local
37 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
39 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
43 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
46 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
47 sunxi_gpio_set_drv(pin, 3);
51 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
52 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
53 sunxi_gpio_set_drv(pin, 3);
55 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
[all …]
H A Dboard.c334 unsigned int pin; in nand_pinmux_setup() local
336 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) in nand_pinmux_setup()
337 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
340 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) in nand_pinmux_setup()
341 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
376 unsigned int pin; in mmc_pinmux_setup() local
382 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { in mmc_pinmux_setup()
383 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); in mmc_pinmux_setup()
384 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); in mmc_pinmux_setup()
385 sunxi_gpio_set_drv(pin, 2); in mmc_pinmux_setup()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3_lcd.dtsi42 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
H A Dat91sam9x5_lcd.dtsi42 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_lcd.dtsi60 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
61 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
62 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
63 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
64 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
65 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
66 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
67 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
68 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
69 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
H A Dat91sam9x5_lcd.dtsi63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rza1.c82 u8 pin: 4; member
99 u16 pin: 4; member
126 { .pin = 0, .func = 1 },
127 { .pin = 1, .func = 1 },
128 { .pin = 2, .func = 1 },
129 { .pin = 3, .func = 1 },
130 { .pin = 4, .func = 1 },
131 { .pin = 5, .func = 1 },
132 { .pin = 6, .func = 1 },
133 { .pin = 7, .func = 1 },
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dkw_gpio.c24 void __set_direction(unsigned pin, int input) in __set_direction() argument
28 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
30 u |= 1 << (pin & 31); in __set_direction()
32 u &= ~(1 << (pin & 31)); in __set_direction()
33 writel(u, GPIO_IO_CONF(pin)); in __set_direction()
35 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
38 static void __set_level(unsigned pin, int high) in __set_level() argument
42 u = readl(GPIO_OUT(pin)); in __set_level()
44 u |= 1 << (pin & 31); in __set_level()
46 u &= ~(1 << (pin & 31)); in __set_level()
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9-pinctrl.dtsi3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
42 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
47 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
60 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
61 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
66 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
67 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
106 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
107 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
[all …]
H A Dexynos7885-pinctrl.dtsi3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
84 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
85 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
90 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
91 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
96 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
97 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
98 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
99 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
[all …]
H A Dexynos5433-pinctrl.dtsi3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
143 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
144 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
145 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
150 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
[all …]
H A Dexynos7-pinctrl.dtsi3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
191 samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
198 samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
203 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
204 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
H A Dexynos850-pinctrl.dtsi3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
108 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
109 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
110 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
116 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
117 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
118 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
124 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
125 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-pinctrl.dtsi3 * Samsung's S5PV210 SoC device tree source - pin control-related
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
279 samsung,pin-function = <S5PV210_PIN_FUNC_2>;
280 samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
281 samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
286 samsung,pin-function = <S5PV210_PIN_FUNC_2>;
287 samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
[all …]
H A Dexynos4x12-pinctrl.dtsi3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
128 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
129 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
130 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
135 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
136 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos4210-pinctrl.dtsi3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
147 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
148 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
149 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
155 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
156 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
161 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
162 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5420-pinctrl.dtsi3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
63 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
64 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
65 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
70 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
71 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
72 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
162 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
163 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5250-pinctrl.dtsi3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
202 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
203 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
204 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
209 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
210 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
211 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
216 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
217 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
H A Dexynos3250-pinctrl.dtsi3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
23 pin- ## _pin { \
25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
26 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
88 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
[all …]
H A Ds3c64xx-pinctrl.dtsi4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
136 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
137 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
142 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
143 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
148 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
149 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
154 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
155 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
[all …]
H A Dexynos5260-pinctrl.dtsi3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
201 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
202 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
203 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
208 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
209 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
210 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
215 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
216 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5410-pinctrl.dtsi3 * Exynos5410 SoC pin-mux and pin-config device tree source
282 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
283 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
284 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
289 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
290 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
291 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
296 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
297 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
298 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
[all …]
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-ssbi-mpp.c167 struct pm8xxx_pin_data *pin) in pm8xxx_mpp_update() argument
175 switch (pin->mode) { in pm8xxx_mpp_update()
177 if (pin->dtest) { in pm8xxx_mpp_update()
179 ctrl = pin->dtest - 1; in pm8xxx_mpp_update()
180 } else if (pin->input && pin->output) { in pm8xxx_mpp_update()
182 if (pin->high_z) in pm8xxx_mpp_update()
184 else if (pin->pullup == 600) in pm8xxx_mpp_update()
186 else if (pin->pullup == 10000) in pm8xxx_mpp_update()
190 } else if (pin->input) { in pm8xxx_mpp_update()
192 if (pin->dtest) in pm8xxx_mpp_update()
[all …]
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dgpio.h18 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) argument
19 #define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) argument
20 #define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) argument
21 #define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) argument
22 #define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) argument
23 #define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) argument
24 #define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) argument
25 #define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) argument
26 #define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) argument
32 void kw_gpio_set_valid(unsigned pin, int mode);
[all …]

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