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Searched refs:phy_write_mmd (Results 1 – 25 of 31) sorted by relevance

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/openbmc/linux/drivers/net/phy/
H A Dmediatek-ge.c27 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in mtk_gephy_config_init()
40 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); in mtk_gephy_config_init()
43 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); in mtk_gephy_config_init()
65 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); in mt7531_phy_config_init()
66 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); in mt7531_phy_config_init()
H A Dnxp-c45-tja11xx.c428 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0, in _nxp_c45_ptp_settime64()
430 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1, in _nxp_c45_ptp_settime64()
432 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0, in _nxp_c45_ptp_settime64()
434 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1, in _nxp_c45_ptp_settime64()
468 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
476 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
531 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
570 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
609 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
652 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
[all …]
H A Dintel-xway.c255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init()
259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init()
277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
H A Ddp83869.c273 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
279 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
285 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
297 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
303 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
308 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
333 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg); in dp83869_set_wol()
706 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, in dp83869_configure_mode()
741 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
753 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
[all …]
H A Dmediatek-ge-soc.c522 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); in tx_r50_fill_result()
769 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); in mt7981_phy_finetune()
802 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); in mt7981_phy_finetune()
805 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); in mt7981_phy_finetune()
806 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); in mt7981_phy_finetune()
807 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); in mt7981_phy_finetune()
808 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); in mt7981_phy_finetune()
809 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); in mt7981_phy_finetune()
810 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); in mt7981_phy_finetune()
811 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); in mt7981_phy_finetune()
[all …]
H A Ddp83tc811.c113 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1, in dp83811_set_wol()
115 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2, in dp83811_set_wol()
117 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3, in dp83811_set_wol()
128 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
131 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
134 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
148 return phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
H A Dmicrel.c784 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); in ksz8061_config_init()
972 return phy_write_mmd(phydev, 2, reg, newval); in ksz9031_of_load_skew_values()
980 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, in ksz9031_center_flp_timing()
985 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, in ksz9031_center_flp_timing()
1001 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, in ksz9031_enable_edpd()
1039 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, in ksz9031_config_rgmii_delay()
1045 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay()
1053 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay()
1061 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, in ksz9031_config_rgmii_delay()
1214 return phy_write_mmd(phydev, 2, reg, newval); in ksz9131_of_load_skew_values()
[all …]
H A Dmicrochip_t1s.c99 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb0_indirect_read()
104 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb0_indirect_read()
153 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_write_cfg_params()
204 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb0_config_init()
H A Dat803x.c466 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], in at803x_set_wol()
1609 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); in qca83xx_config_init()
1612 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); in qca83xx_config_init()
1714 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, in qca808x_phy_fast_retrain_config()
1716 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, in qca808x_phy_fast_retrain_config()
1718 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, in qca808x_phy_fast_retrain_config()
1720 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, in qca808x_phy_fast_retrain_config()
1722 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, in qca808x_phy_fast_retrain_config()
1724 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config()
1726 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, in qca808x_phy_fast_retrain_config()
[all …]
H A Ddp83822.c139 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, in dp83822_set_wol()
141 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, in dp83822_set_wol()
143 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, in dp83822_set_wol()
154 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
157 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
160 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
174 return phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
593 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | in dp83822_resume()
H A Ddp83867.c212 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, in dp83867_set_wol()
214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, in dp83867_set_wol()
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, in dp83867_set_wol()
225 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, in dp83867_set_wol()
227 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, in dp83867_set_wol()
229 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, in dp83867_set_wol()
251 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); in dp83867_set_wol()
840 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
849 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init()
894 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); in dp83867_config_init()
[all …]
H A Dsmsc.c280 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_phy_config_init()
286 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR, in lan874x_phy_config_init()
376 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
382 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
390 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask); in lan874x_set_wol_pattern()
400 phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 0); in lan874x_set_wol_pattern()
486 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, in lan874x_set_wol()
493 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_set_wol()
H A Dbcm87xx.c69 ret = phy_write_mmd(phydev, devid, reg, val); in bcm87xx_of_reg_init()
155 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
159 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
H A Ddp83td510.c61 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
73 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
H A Dmarvell-88x2222.c80 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
201 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
204 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
207 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
H A Dphy-c45.c167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1302 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1334 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
H A Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
H A Daquantia_main.c298 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr()
303 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, in aqr_config_intr()
308 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, in aqr_config_intr()
H A Dmarvell-88q2xxx.c35 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_soft_reset()
H A Dmarvell10g.c265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1311 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
H A Daquantia_hwmon.c79 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
H A Dadin1100.c145 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_set_powerdown_mode()
H A Dadin.c296 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
323 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
H A Dphy-core.c645 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) in phy_write_mmd() function
655 EXPORT_SYMBOL(phy_write_mmd);
H A Dmicrochip.c329 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG, in lan88xx_config_init()

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