| /openbmc/linux/drivers/pci/controller/dwc/ |
| H A D | pcie-tegra194.c | 300 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
306 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
315 static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie) in tegra_pcie_icc_set() argument
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
328 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
333 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); in tegra_pcie_icc_set()
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| H A D | pcie-intel-gw.c | 84 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
86 writel(val, pcie->app_base + ofs); in pcie_app_wr()
89 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
92 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
95 static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) in pcie_rc_cfg_rd() argument
97 return dw_pcie_readl_dbi(&pcie->pci, ofs); in pcie_rc_cfg_rd()
100 static inline void pcie_rc_cfg_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_rc_cfg_wr() argument
102 dw_pcie_writel_dbi(&pcie->pci, ofs, val); in pcie_rc_cfg_wr()
105 static void pcie_rc_cfg_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_rc_cfg_wr_mask() argument
108 pcie_update_bits(pcie->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
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| H A D | pcie-visconti.c | 97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
114 static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_mpu_writel() argument
116 writel_relaxed(val, pcie->mpu_base + reg); in visconti_mpu_writel()
119 static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg) in visconti_mpu_readl() argument
121 return readl_relaxed(pcie->mpu_base + reg); in visconti_mpu_readl()
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| H A D | pcie-uniphier.c | 75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
104 val = readl(pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
109 writel(val, pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
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| H A D | pcie-qcom.c | 222 int (*get_resources)(struct qcom_pcie *pcie);
223 int (*init)(struct qcom_pcie *pcie);
224 int (*post_init)(struct qcom_pcie *pcie);
225 void (*deinit)(struct qcom_pcie *pcie);
226 void (*ltssm_enable)(struct qcom_pcie *pcie);
227 int (*config_sid)(struct qcom_pcie *pcie);
250 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
252 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
256 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) in qcom_ep_reset_deassert() argument
260 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
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| H A D | pcie-keembay.c | 72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
106 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
109 val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); in keembay_pcie_link_up()
116 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_start_link() local
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| H A D | pci-layerscape.c | 52 #define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr)
55 static bool ls_pcie_is_bridge(struct ls_pcie *pcie) in ls_pcie_is_bridge() argument
57 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
67 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) in ls_pcie_clear_multifunction() argument
69 struct dw_pcie *pci = pcie->pci; in ls_pcie_clear_multifunction()
75 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) in ls_pcie_drop_msg_tlp() argument
78 struct dw_pcie *pci = pcie->pci; in ls_pcie_drop_msg_tlp()
86 static void ls_pcie_fix_error_response(struct ls_pcie *pcie) in ls_pcie_fix_error_response() argument
88 struct dw_pcie *pci = pcie->pci; in ls_pcie_fix_error_response()
93 static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) in ls_pcie_pf_readl() argument
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| /openbmc/u-boot/drivers/pci/ |
| H A D | pcie_layerscape.c | 25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) in dbi_readl() argument
27 return in_le32(pcie->dbi + offset); in dbi_readl()
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, in dbi_writel() argument
33 out_le32(pcie->dbi + offset, value); in dbi_writel()
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) in ctrl_readl() argument
38 if (pcie->big_endian) in ctrl_readl()
39 return in_be32(pcie->ctrl + offset); in ctrl_readl()
41 return in_le32(pcie->ctrl + offset); in ctrl_readl()
44 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, in ctrl_writel() argument
47 if (pcie->big_endian) in ctrl_writel()
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| H A D | pci-aardvark.c | 150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) in advk_writel() argument
152 writel(val, pcie->base + reg); in advk_writel()
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg) in advk_readl() argument
157 return readl(pcie->base + reg); in advk_readl()
191 static int pcie_advk_wait_pio(struct pcie_advk *pcie) in pcie_advk_wait_pio() argument
197 start = advk_readl(pcie, PIO_START); in pcie_advk_wait_pio()
198 isr = advk_readl(pcie, PIO_ISR); in pcie_advk_wait_pio()
208 dev_err(pcie->dev, "config read/write timed out\n"); in pcie_advk_wait_pio()
220 static int pcie_advk_check_pio_status(struct pcie_advk *pcie, in pcie_advk_check_pio_status() argument
228 reg = advk_readl(pcie, PIO_STAT); in pcie_advk_check_pio_status()
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| H A D | pcie_intel_fpga.c | 37 #define RP_CFG_ADDR(pcie, reg) \ argument
38 ((pcie->hip_base) + (reg) + (1 << 20))
41 #define TLP_CFGRD_DW0(pcie, bus) \ argument
42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
46 #define TLP_CFGWR_DW0(pcie, bus) \ argument
47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
51 #define TLP_CFG_DW1(pcie, tag, be) \ argument
52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
62 #define IS_ROOT_PORT(pcie, bdf) \ argument
63 ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
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| H A D | pci_mvebu.c | 91 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) in mvebu_pcie_link_up() argument
94 val = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_link_up()
98 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) in mvebu_pcie_set_local_bus_nr() argument
102 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
105 writel(stat, pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
108 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno) in mvebu_pcie_set_local_dev_nr() argument
112 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_dev_nr()
115 writel(stat, pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_dev_nr()
118 static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie) in mvebu_pcie_get_local_bus_nr() argument
122 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_get_local_bus_nr()
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| H A D | pci_tegra.c | 195 struct tegra_pcie *pcie; member
240 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, in afi_writel() argument
243 writel(value, pcie->afi.start + offset); in afi_writel()
246 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
248 return readl(pcie->afi.start + offset); in afi_readl()
251 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, in pads_writel() argument
254 writel(value, pcie->pads.start + offset); in pads_writel()
258 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) in pads_readl() argument
260 return readl(pcie->pads.start + offset); in pads_readl()
283 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, in tegra_pcie_conf_address() argument
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | pci-aardvark.c | 293 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
295 writel(val, pcie->base + reg); in advk_writel()
298 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
300 return readl(pcie->base + reg); in advk_readl()
303 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
308 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
313 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
316 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
320 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
330 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
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| H A D | pcie-xilinx-nwl.c | 176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
200 static int nwl_wait_for_link(struct nwl_pcie *pcie) in nwl_wait_for_link() argument
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
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| H A D | pcie-altera.c | 44 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
45 (((pcie)->hip_base) + (reg) + (1 << 20))
46 #define S10_RP_SECONDARY(pcie) \ argument
47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
98 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
99 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
101 bool (*get_link_status)(struct altera_pcie *pcie);
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| H A D | pcie-mediatek-gen3.c | 199 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_config_tlp_header() local
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); in mtk_pcie_config_tlp_header()
214 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus() local
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; in mtk_pcie_map_bus()
244 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, in mtk_pcie_set_trans_table() argument
268 dev_err(pcie->dev, "illegal table size %#llx\n", in mtk_pcie_set_trans_table()
273 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET; in mtk_pcie_set_trans_table()
289 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", in mtk_pcie_set_trans_table()
300 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", in mtk_pcie_set_trans_table()
306 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) in mtk_pcie_enable_msi() argument
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| H A D | pci-tegra.c | 362 struct tegra_pcie *pcie; member
375 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
378 writel(value, pcie->afi + offset); in afi_writel()
381 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
383 return readl(pcie->afi + offset); in afi_readl()
386 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
389 writel(value, pcie->pads + offset); in pads_writel()
392 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) in pads_readl() argument
394 return readl(pcie->pads + offset); in pads_readl()
429 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus() local
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| H A D | pcie-iproc.c | 400 struct iproc_pcie *pcie = bus->sysdata; in iproc_data() local
401 return pcie; in iproc_data()
409 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, in iproc_pcie_reg_offset() argument
412 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
415 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, in iproc_pcie_read_reg() argument
418 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_read_reg()
423 return readl(pcie->base + offset); in iproc_pcie_read_reg()
426 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, in iproc_pcie_write_reg() argument
429 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_write_reg()
434 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
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| H A D | pcie-brcmstb.c | 181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
221 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
222 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
265 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
266 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
271 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
273 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
342 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
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| H A D | pcie-rcar-host.c | 46 struct rcar_pcie pcie; member
98 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
101 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
123 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
130 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); in rcar_pci_write_reg_workaround()
132 rcar_pci_write_reg(pcie, val, reg); in rcar_pci_write_reg_workaround()
137 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, in rcar_pci_read_reg_workaround() argument
144 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); in rcar_pci_read_reg_workaround()
149 *val = rcar_pci_read_reg(pcie, reg); in rcar_pci_read_reg_workaround()
159 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
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| H A D | pcie-xilinx.c | 113 static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) in pcie_read() argument
115 return readl(pcie->reg_base + reg); in pcie_read()
118 static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
120 writel(val, pcie->reg_base + reg); in pcie_write()
123 static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) in xilinx_pcie_link_up() argument
125 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & in xilinx_pcie_link_up()
133 static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie *pcie) in xilinx_pcie_clear_err_interrupts() argument
135 struct device *dev = pcie->dev; in xilinx_pcie_clear_err_interrupts()
136 unsigned long val = pcie_read(pcie, XILINX_PCIE_REG_RPEFR); in xilinx_pcie_clear_err_interrupts()
141 pcie_write(pcie, XILINX_PCIE_RPEFR_ALL_MASK, in xilinx_pcie_clear_err_interrupts()
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| /openbmc/linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil-host.c | 50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
71 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
85 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
86 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
87 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
102 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
103 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_pcie_isr()
108 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
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| H A D | pcie-mobiveil.c | 28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
99 u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size) in mobiveil_csr_read() argument
105 addr = mobiveil_pcie_comp_addr(pcie, off); in mobiveil_csr_read()
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| /openbmc/linux/drivers/pci/controller/cadence/ |
| H A D | pcie-cadence.c | 11 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
19 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
24 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
27 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
47 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
48 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
76 if (pcie->is_rc) { in cdns_pcie_set_outbound_region()
89 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0); in cdns_pcie_set_outbound_region()
90 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); in cdns_pcie_set_outbound_region()
93 if (pcie->ops->cpu_addr_fixup) in cdns_pcie_set_outbound_region()
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| H A D | pci-j721e.c | 27 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
80 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
82 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
85 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
88 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
91 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
93 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
96 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_intd_writel() argument
99 writel(value, pcie->intd_cfg_base + offset); in j721e_pcie_intd_writel()
104 struct j721e_pcie *pcie = priv; in j721e_pcie_link_irq_handler() local
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