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/openbmc/linux/drivers/clk/ingenic/
H A Djz4755-cgu.c53 .parents = { JZ4755_CLK_EXT, },
78 .parents = { JZ4755_CLK_PLL, },
87 .parents = { JZ4755_CLK_EXT, },
96 .parents = { JZ4755_CLK_PLL, },
105 .parents = { JZ4755_CLK_PLL, },
114 .parents = { JZ4755_CLK_PLL, },
123 .parents = { JZ4755_CLK_PLL, },
132 .parents = { JZ4755_CLK_PLL, },
141 .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, },
149 .parents = { JZ4755_CLK_PLL_HALF, },
[all …]
H A Djz4780-cgu.c294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
349 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
360 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
366 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
[all …]
H A Djz4760-cgu.c94 .parents = { JZ4760_CLK_EXT },
119 .parents = { JZ4760_CLK_EXT },
149 .parents = { JZ4760_CLK_PLL0, },
157 .parents = { JZ4760_CLK_PLL0, },
165 .parents = { JZ4760_CLK_PLL0, },
173 .parents = { JZ4760_CLK_PLL0, },
186 .parents = { JZ4760_CLK_PLL0, },
194 .parents = { JZ4760_CLK_PLL0, },
205 .parents = { JZ4760_CLK_PLL0 },
216 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
[all …]
H A Djz4770-cgu.c104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
157 .parents = { JZ4770_CLK_PLL0, },
165 .parents = { JZ4770_CLK_PLL0, },
173 .parents = { JZ4770_CLK_PLL0, },
182 .parents = { JZ4770_CLK_PLL0, },
190 .parents = { JZ4770_CLK_PLL0, },
199 .parents = { JZ4770_CLK_PLL0, },
210 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
217 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
[all …]
H A Dx1830-cgu.c114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
229 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
241 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
247 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
[all …]
H A Djz4725b-cgu.c56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
95 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
104 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
113 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
127 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
146 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
153 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
160 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
[all …]
H A Dx1000-cgu.c219 .parents = { X1000_CLK_EXCLK },
242 .parents = { X1000_CLK_EXCLK },
267 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
275 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
281 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
292 .parents = { X1000_CLK_CPUMUX },
304 .parents = { X1000_CLK_CPUMUX },
310 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
317 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
323 .parents = { X1000_CLK_AHB2PMUX },
[all …]
H A Djz4740-cgu.c71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
142 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
161 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
167 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
175 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
[all …]
/openbmc/openbmc/poky/meta/recipes-kernel/linux/
H A Dkernel-devsrc.bb63 cp --parents $(find -type f -name "Makefile*" -o -name "Kconfig*") $kerneldir/build
64 cp --parents $(find -type f -name "Build" -o -name "Build.include") $kerneldir/build
95 cp -a --parents scripts/module.lds $kerneldir/build/ 2>/dev/null || :
110 cp -a --parents arch/powerpc/lib/crtsavres.[So] $kerneldir/build/
116 cp -a --parents arch/${ARCH}/kernel/vdso/vdso.lds $kerneldir/build/
120 cp -a --parents arch/powerpc/kernel/vdso32/vdso32.lds $kerneldir/build 2>/dev/null || :
121 cp -a --parents arch/powerpc/kernel/vdso64/vdso64.lds $kerneldir/build 2>/dev/null || :
123 cp -a --parents arch/powerpc/kernel/vdso/vdso*.lds $kerneldir/build 2>/dev/null || :
131 cp -a --parents include/generated/autoconf.h $kerneldir/build 2>/dev/null || :
147 cp -a --parents Kbuild $kerneldir/build 2>/dev/null || :
[all …]
/openbmc/linux/drivers/clk/st/
H A Dclkgen-mux.c21 const char **parents; in clkgen_mux_get_parents() local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
29 if (!parents) in clkgen_mux_get_parents()
32 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
33 return parents; in clkgen_mux_get_parents()
57 const char **parents; in st_of_clkgen_mux_setup() local
76 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgen_mux_setup()
77 if (IS_ERR(parents)) { in st_of_clkgen_mux_setup()
79 __func__, PTR_ERR(parents)); in st_of_clkgen_mux_setup()
83 clk = clk_register_mux(NULL, np->name, parents, num_parents, in st_of_clkgen_mux_setup()
[all …]
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.h29 u8 parents[4]; member
37 .parents = { [0] = _parent }, \
45 .parents = { [0] = _parent }, \
53 .parents = { [0] = _parent }, \
61 .parents = { [0] = _parent }, \
69 .parents = { __VA_ARGS__ }, \
78 .parents = { __VA_ARGS__ }, \
86 .parents = { __VA_ARGS__ }, \
95 .parents = { __VA_ARGS__ }, \
103 .parents = { [0] = _parent }, \
H A Dclk-starfive-jh7110-aon.c88 struct clk_parent_data parents[4] = {}; in jh7110_aoncrg_probe() local
92 .parent_data = parents, in jh7110_aoncrg_probe()
101 unsigned int pidx = jh7110_aonclk_data[idx].parents[i]; in jh7110_aoncrg_probe()
104 parents[i].hw = &priv->reg[pidx].hw; in jh7110_aoncrg_probe()
106 parents[i].fw_name = "osc"; in jh7110_aoncrg_probe()
108 parents[i].fw_name = "gmac0_rmii_refin"; in jh7110_aoncrg_probe()
110 parents[i].fw_name = "gmac0_rgmii_rxin"; in jh7110_aoncrg_probe()
112 parents[i].fw_name = "stg_axiahb"; in jh7110_aoncrg_probe()
114 parents[i].fw_name = "apb_bus"; in jh7110_aoncrg_probe()
116 parents[i].fw_name = "gmac0_gtxclk"; in jh7110_aoncrg_probe()
[all …]
H A Dclk-starfive-jh7100-audio.c116 struct clk_parent_data parents[4] = {}; in jh7100_audclk_probe() local
120 .parent_data = parents, in jh7100_audclk_probe()
128 unsigned int pidx = jh7100_audclk_data[idx].parents[i]; in jh7100_audclk_probe()
131 parents[i].hw = &priv->reg[pidx].hw; in jh7100_audclk_probe()
133 parents[i].fw_name = "audio_src"; in jh7100_audclk_probe()
135 parents[i].fw_name = "audio_12288"; in jh7100_audclk_probe()
137 parents[i].fw_name = "dom7ahb_bus"; in jh7100_audclk_probe()
H A Dclk-starfive-jh7110-sys.c475 struct clk_parent_data parents[4] = {}; in jh7110_syscrg_probe() local
479 .parent_data = parents, in jh7110_syscrg_probe()
488 unsigned int pidx = jh7110_sysclk_data[idx].parents[i]; in jh7110_syscrg_probe()
491 parents[i].hw = &priv->reg[pidx].hw; in jh7110_syscrg_probe()
493 parents[i].fw_name = "osc"; in jh7110_syscrg_probe()
495 parents[i].fw_name = "gmac1_rmii_refin"; in jh7110_syscrg_probe()
497 parents[i].fw_name = "gmac1_rgmii_rxin"; in jh7110_syscrg_probe()
499 parents[i].fw_name = "i2stx_bclk_ext"; in jh7110_syscrg_probe()
501 parents[i].fw_name = "i2stx_lrck_ext"; in jh7110_syscrg_probe()
503 parents[i].fw_name = "i2srx_bclk_ext"; in jh7110_syscrg_probe()
[all …]
/openbmc/linux/drivers/clk/zynqmp/
H A Dclkc.c99 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; member
123 const char * const *parents,
311 const char * const *parents, in zynqmp_clk_register_fixed_factor() argument
335 parents[0], in zynqmp_clk_register_fixed_factor()
476 static int __zynqmp_clock_get_parents(struct clock_parent *parents, in __zynqmp_clock_get_parents() argument
483 for (i = 0; i < ARRAY_SIZE(response->parents); i++) { in __zynqmp_clock_get_parents()
484 if (response->parents[i] == NA_PARENT) in __zynqmp_clock_get_parents()
487 parent = &parents[i]; in __zynqmp_clock_get_parents()
488 parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]); in __zynqmp_clock_get_parents()
489 if (response->parents[i] == DUMMY_PARENT) { in __zynqmp_clock_get_parents()
[all …]
H A Dclk-zynqmp.h71 const char * const *parents,
76 const char * const *parents,
82 const char * const *parents,
87 const char * const *parents,
93 const char * const *parents,
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sun8i-mbus.c27 const char **parents; in sun8i_a23_mbus_setup() local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL); in sun8i_a23_mbus_setup()
38 if (!parents) in sun8i_a23_mbus_setup()
60 of_clk_parent_fill(node, parents, num_parents); in sun8i_a23_mbus_setup()
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents, in sun8i_a23_mbus_setup()
89 kfree(parents); /* parents is deep copied */ in sun8i_a23_mbus_setup()
107 kfree(parents); in sun8i_a23_mbus_setup()
H A Dclk-sun4i-display.c19 u8 parents; member
104 const char *parents[4]; in sun4i_a10_display_init() local
123 ret = of_clk_parent_fill(node, parents, data->parents); in sun4i_a10_display_init()
124 if (ret != data->parents) { in sun4i_a10_display_init()
158 parents, data->parents, in sun4i_a10_display_init()
224 .parents = 4,
242 .parents = 3,
/openbmc/linux/drivers/clk/tegra/
H A Dclk-bpmp.c23 unsigned int parents[MRQ_CLK_MAX_PARENTS]; member
35 unsigned int *parents; member
208 request.parent_id = clk->parents[index]; in tegra_bpmp_clk_set_parent()
249 if (clk->parents[i] == response.parent_id) in tegra_bpmp_clk_get_parent()
374 info->parents[i] = response.parents[i]; in tegra_bpmp_clk_get_info()
418 dev_printk(level, bpmp->dev, " %03u\n", info->parents[i]); in tegra_bpmp_clk_info_dump()
509 const char **parents; in tegra_bpmp_clk_register() local
520 clk->parents = devm_kcalloc(bpmp->dev, info->num_parents, in tegra_bpmp_clk_register()
521 sizeof(*clk->parents), GFP_KERNEL); in tegra_bpmp_clk_register()
522 if (!clk->parents) in tegra_bpmp_clk_register()
[all …]
/openbmc/phosphor-logging/tools/
H A Delog-gen.py134 parents = dict()
166 parents,
171 if not check_error_inheritance(errors, parents):
175 errors = order_inherited_errors(errors, parents)
189 parents=parents,
215 parents,
236 parents[fullname] = None
257 parents[fullname] = match["inherits"][0]
/openbmc/linux/drivers/clk/imx/
H A Dclk.h148 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
149 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
151 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
152 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
154 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
155 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
199 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ argument
200 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
202 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ argument
203 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy_clk.c148 const char *parents[2]; in sun8i_phy_clk_create() local
150 parents[0] = __clk_get_name(phy->clk_pll0); in sun8i_phy_clk_create()
151 if (!parents[0]) in sun8i_phy_clk_create()
155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
156 if (!parents[1]) in sun8i_phy_clk_create()
166 init.parent_names = parents; in sun8i_phy_clk_create()
/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c448 int *parents; in meson_mux_get_parent() local
454 parents = meson_vpu_mux_parents; in meson_mux_get_parent()
458 parents = meson_vpu_0_1_mux_parents; in meson_mux_get_parent()
462 parents = meson_vpu_0_1_mux_parents; in meson_mux_get_parent()
466 parents = meson_vapb_sel_mux_parents; in meson_mux_get_parent()
470 parents = meson_vapb_0_1_mux_parents; in meson_mux_get_parent()
474 parents = meson_vapb_0_1_mux_parents; in meson_mux_get_parent()
484 __func__, id, parents[reg], reg); in meson_mux_get_parent()
486 return parents[reg]; in meson_mux_get_parent()
496 int *parents; in meson_mux_set_parent() local
[all …]
/openbmc/linux/drivers/clk/x86/
H A Dclk-pmc-atom.c47 struct clk_plt_fixed **parents; member
248 plt_clk_unregister_fixed_rate(data->parents[i]); in plt_clk_unregister_fixed_rate_loop()
279 data->parents = devm_kcalloc(&pdev->dev, nparents, in plt_clk_register_parents()
280 sizeof(*data->parents), GFP_KERNEL); in plt_clk_register_parents()
281 if (!data->parents) in plt_clk_register_parents()
290 data->parents[i] = in plt_clk_register_parents()
294 if (IS_ERR(data->parents[i])) { in plt_clk_register_parents()
295 err = PTR_ERR(data->parents[i]); in plt_clk_register_parents()
/openbmc/pldm/host-bmc/
H A Dutils.cpp18 Entities parents{}; in getParentEntites() local
21 parents.push_back(et[0]); in getParentEntites()
25 for (auto it = parents.begin(); it != parents.end(); in getParentEntites()
26 it = found ? parents.erase(it) : std::next(it)) in getParentEntites()
56 return parents; in getParentEntites()

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