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Searched refs:int_level (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/hw/net/
H A Dsmc91c111.c55 uint8_t int_level; member
83 VMSTATE_UINT8(int_level, smc91c111_state),
127 s->int_level |= INT_TX_EMPTY; in smc91c111_update()
129 s->int_level |= INT_TX; in smc91c111_update()
130 level = (s->int_level & s->int_mask) != 0; in smc91c111_update()
176 s->int_level |= INT_ALLOC; in smc91c111_tx_alloc()
198 s->int_level |= INT_RCV; in smc91c111_pop_rx_fifo()
200 s->int_level &= ~INT_RCV; in smc91c111_pop_rx_fifo()
313 s->int_level = INT_TX_EMPTY; in smc91c111_reset()
404 s->int_level &= ~INT_ALLOC; in smc91c111_writeb()
[all …]
/openbmc/qemu/hw/char/
H A Dpl011.c136 flags = s->int_level & s->int_enabled; in pl011_update()
193 s->int_level |= INT_RX; in pl011_fifo_rx_put()
243 s->int_level |= INT_TX; in pl011_write_txdata()
261 s->int_level &= ~INT_RX; in pl011_read_rxdata()
308 r = s->int_level; in pl011_read()
311 r = s->int_level & s->int_enabled; in pl011_read()
393 il = s->int_level & ~(INT_DSR | INT_DCD | INT_CTS | INT_RI); in pl011_loopback_mdmctrl()
400 s->int_level = il; in pl011_loopback_mdmctrl()
470 s->int_level &= ~value; in pl011_write()
589 VMSTATE_UINT32(int_level, PL011State),
[all …]
/openbmc/qemu/rust/hw/char/pl011/src/
H A Ddevice.rs74 pub int_level: u32, field
203 self.int_level &= !registers::INT_RX; in read()
223 Ok(RIS) => self.int_level.into(), in read()
224 Ok(MIS) => u64::from(self.int_level & self.int_enabled), in read()
254 self.int_level |= registers::INT_TX; in write()
314 self.int_level &= !value; in write()
379 let mut il = self.int_level; in loopback_mdmctrl()
395 self.int_level = il; in loopback_mdmctrl()
431 self.int_level = 0; in reset()
493 self.int_level |= registers::INT_RX; in put_fifo()
[all …]
H A Ddevice_class.rs61 vmstate_uint32!(int_level, PL011State),
/openbmc/qemu/hw/timer/
H A Dsh_timer.c43 int int_level; member
54 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); in sh_timer_update()
59 s->old_level = s->int_level; in sh_timer_update()
60 s->int_level = new_level; in sh_timer_update()
73 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); in sh_timer_read()
167 s->int_level = 0; in sh_timer_write()
224 s->int_level = s->enabled; in sh_timer_tick()
H A Darm_timer.c37 int int_level; member
46 if (s->int_level && (s->control & TIMER_CTRL_IE)) { in arm_timer_update()
66 return s->int_level; in arm_timer_read()
70 return s->int_level; in arm_timer_read()
140 s->int_level = 0; in arm_timer_write()
158 s->int_level = 1; in arm_timer_tick()
169 VMSTATE_INT32(int_level, arm_timer_state),
/openbmc/qemu/hw/arm/
H A Dintegratorcp.c52 uint32_t int_level; member
75 VMSTATE_UINT32(int_level, IntegratorCMState),
130 return s->int_level & s->irq_enabled; in integratorcm_read()
132 return s->int_level; in integratorcm_read()
136 return s->int_level & 1; in integratorcm_read()
138 return s->int_level & s->fiq_enabled; in integratorcm_read()
140 return s->int_level; in integratorcm_read()
186 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) in integratorcm_update()
237 s->int_level |= (value & 1); in integratorcm_write()
241 s->int_level &= ~(value & 1); in integratorcm_write()
/openbmc/linux/arch/sparc/include/asm/
H A Dhead_32.h72 #define TRAP_ENTRY_INTERRUPT(int_level) \ argument
73 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
/openbmc/qemu/include/hw/char/
H A Dpl011.h41 uint32_t int_level; member
/openbmc/linux/drivers/staging/vme_user/
H A Dvme_fake.c73 int int_level; member
101 vme_irq_handler(fake_bridge, bridge->int_level, bridge->int_statid); in fake_VIRQ_tasklet()
136 bridge->int_level = level; in fake_irq_generate()