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Searched refs:imm8 (Results 1 – 23 of 23) sorted by relevance

/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc256 /* TCG private relocation type: add with pc+imm8 */
259 /* TCG private relocation type: vldr with imm8 << 2 */
368 uint32_t rot, imm8;
377 imm8 = imm >> rot;
379 if ((imm8 & ~0xff) == 0) {
388 imm8 = rol32(imm, rot);
389 if ((imm8 & ~0xff) == 0) {
398 return rot << 7 | imm8;
414 static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
418 *imm8 = v16 & 0xff;
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/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc176 static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
180 *imm8 = v16 & 0xff;
184 *imm8 = v16 >> 8;
191 static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
195 *imm8 = v32 & 0xff;
199 *imm8 = (v32 >> 8) & 0xff;
203 *imm8 = (v32 >> 16) & 0xff;
207 *imm8 = v32 >> 24;
214 static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
218 *imm8 = (v32 >> 8) & 0xff;
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/openbmc/linux/arch/arm/kernel/
H A Dphys2virt.S80 @ as imm4:i:imm3:imm8)
84 @ MOVW | 1 1 1 1 0 | i | 1 0 0 1 0 0 | imm4 || 0 | imm3 | Rd | imm8 |
94 @ order bits, which can be patched into imm8 directly (and i:imm3
99 @ MOV | 1 1 1 1 0 | i | 0 0 0 1 0 0 1 1 1 1 || 0 | imm3 | Rd | imm8 |
100 @ MVN | 1 1 1 1 0 | i | 0 0 0 1 1 0 1 1 1 1 || 0 | imm3 | Rd | imm8 |
105 ubfx r6, r6, #21, #8 @ put bits 28:21 into the MOVW imm8 field
/openbmc/linux/arch/riscv/net/
H A Dbpf_jit.h697 static inline u16 rvc_lwsp(u8 rd, u32 imm8) in rvc_lwsp() argument
701 imm = ((imm8 & 0xc0) >> 6) | (imm8 & 0x3c); in rvc_lwsp()
725 static inline u16 rvc_swsp(u32 imm8, u8 rs2) in rvc_swsp() argument
729 imm = (imm8 & 0x3c) | ((imm8 & 0xc0) >> 6); in rvc_swsp()
864 static inline u16 rvc_ld(u8 rd, u32 imm8, u8 rs1) in rvc_ld() argument
868 imm_hi = (imm8 & 0x38) >> 3; in rvc_ld()
869 imm_lo = (imm8 & 0xc0) >> 6; in rvc_ld()
873 static inline u16 rvc_sd(u8 rs1, u32 imm8, u8 rs2) in rvc_sd() argument
877 imm_hi = (imm8 & 0x38) >> 3; in rvc_sd()
878 imm_lo = (imm8 & 0xc0) >> 6; in rvc_sd()
/openbmc/qemu/target/avr/
H A Dinsn.decode36 %imm8 8:4 0:4
47 @op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8
/openbmc/qemu/target/rx/
H A Dinsns.decode337 # MOV.b #imm8, dsp5[rd]
339 # MOV.w #imm8, dsp5[rd]
341 # MOV.l #imm8, dsp5[rd]
343 # MOV.l #imm8, rd
/openbmc/linux/arch/riscv/kernel/
H A Dmodule.c77 u16 imm8 = (offset & 0x100) << (12 - 8); in apply_r_riscv_rvc_branch_rela() local
84 imm8 | imm7_6 | imm5 | imm4_3 | imm2_1; in apply_r_riscv_rvc_branch_rela()
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-vfp.c62 uint64_t vfp_expand_imm(int size, uint8_t imm8) in vfp_expand_imm() argument
68 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | in vfp_expand_imm()
69 (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | in vfp_expand_imm()
70 extract32(imm8, 0, 6); in vfp_expand_imm()
74 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | in vfp_expand_imm()
75 (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | in vfp_expand_imm()
76 (extract32(imm8, 0, 6) << 3); in vfp_expand_imm()
80 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | in vfp_expand_imm()
81 (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | in vfp_expand_imm()
82 (extract32(imm8, 0, 6) << 6); in vfp_expand_imm()
H A Dtranslate.h404 uint64_t vfp_expand_imm(int size, uint8_t imm8);
/openbmc/qemu/tests/tcg/i386/
H A Dx86.csv14 # 1. The Intel manual instruction mnemonic. For example, "SHR r/m32, imm8".
16 # 2. The Go assembler instruction mnemonic. For example, "SHRL imm8, r/m32".
18 # 3. The GNU binutils instruction mnemonic. For example, "shrl imm8, r/m32".
31 # the Intel mnemonic. For example, "rw,r" to denote that "SHR r/m32, imm8"
54 # Immediate values: imm8, imm8u, imm16, imm16u, imm32, imm64.
184 "ADC AL, imm8","ADCB imm8, AL","adcb imm8, AL","14 ib","V","V","","","rw,r","Y","8"
185 "ADC r/m8, imm8","ADCB imm8, r/m8","adcb imm8, r/m8","80 /2 ib","V","V","","","rw,r","Y","8"
186 "ADC r/m8, imm8","ADCB imm8, r/m8","adcb imm8, r/m8","82 /2 ib","V","N.S.","","","rw,r","Y","8"
187 "ADC r/m8, imm8","ADCB imm8, r/m8","adcb imm8, r/m8","REX 80 /2 ib","N.E.","V","","pseudo64","rw,r"…
194 "ADC r/m32, imm8","ADCL imm8, r/m32","adcl imm8, r/m32","83 /2 ib","V","V","","operand32","rw,r","Y…
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/openbmc/linux/arch/arm/net/
H A Dbpf_jit_32.c321 static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8) in arm_bpf_ldst_imm8() argument
324 if (imm8 >= 0) in arm_bpf_ldst_imm8()
327 imm8 = -imm8; in arm_bpf_ldst_imm8()
328 return op | (imm8 & 0xf0) << 4 | (imm8 & 0x0f); in arm_bpf_ldst_imm8()
/openbmc/linux/drivers/net/ethernet/netronome/nfp/bpf/
H A Djit.c488 u8 areg, u8 bmask, u8 breg, u8 shift, bool imm8, in __emit_ld_field() argument
498 FIELD_PREP(OP_LDF_I8, imm8) | in __emit_ld_field()
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc970 /* imm8 operand: all output lanes selected from input lane 0. */
1000 tcg_out8(s, 0); /* imm8 */
1005 tcg_out8(s, 0); /* imm8 */
/openbmc/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc2097 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc2212 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc2598 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc2866 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc2966 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc2785 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc4325 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dxtensa-modules.c.inc10748 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc12465 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc43702 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },