| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-imx7d.c | 377 static struct clk_hw **hws; variable
385 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx7d_clocks_init()
391 hws = clk_hw_data->hws; in imx7d_clocks_init()
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
394 hws[IMX7D_OSC_24M_CLK] = imx_get_clk_hw_by_name(ccm_node, "osc"); in imx7d_clocks_init()
395 hws[IMX7D_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
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| H A D | clk-imx8mq.c | 282 static struct clk_hw **hws; variable
291 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL); in imx8mq_clocks_probe()
296 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
298 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
299 hws[IMX8MQ_CLK_32K] = imx_get_clk_hw_by_name(np, "ckil"); in imx8mq_clocks_probe()
300 hws[IMX8MQ_CLK_25M] = imx_get_clk_hw_by_name(np, "osc_25m"); in imx8mq_clocks_probe()
301 hws[IMX8MQ_CLK_27M] = imx_get_clk_hw_by_name(np, "osc_27m"); in imx8mq_clocks_probe()
302 hws[IMX8MQ_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); in imx8mq_clocks_probe()
303 hws[IMX8MQ_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); in imx8mq_clocks_probe()
304 hws[IMX8MQ_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); in imx8mq_clocks_probe()
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| H A D | clk-imx6sx.c | 85 static struct clk_hw **hws; variable
125 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sx_clocks_init()
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
133 hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sx_clocks_init()
135 hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx6sx_clocks_init()
136 hws[IMX6SX_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); in imx6sx_clocks_init()
139 hws[IMX6SX_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); in imx6sx_clocks_init()
140 hws[IMX6SX_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); in imx6sx_clocks_init()
143 hws[IMX6SX_CLK_ANACLK1] = imx_get_clk_hw_by_name(ccm_node, "anaclk1"); in imx6sx_clocks_init()
144 hws[IMX6SX_CLK_ANACLK2] = imx_get_clk_hw_by_name(ccm_node, "anaclk2"); in imx6sx_clocks_init()
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| H A D | clk-imx8mp.c | 406 static struct clk_hw **hws; variable
427 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL); in imx8mp_clocks_probe()
432 hws = clk_hw_data->hws; in imx8mp_clocks_probe()
434 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
435 hws[IMX8MP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); in imx8mp_clocks_probe()
436 hws[IMX8MP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); in imx8mp_clocks_probe()
437 hws[IMX8MP_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); in imx8mp_clocks_probe()
438 hws[IMX8MP_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); in imx8mp_clocks_probe()
439 hws[IMX8MP_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); in imx8mp_clocks_probe()
440 hws[IMX8MP_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); in imx8mp_clocks_probe()
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| H A D | clk-imx8mm.c | 297 static struct clk_hw **hws; variable
306 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx8mm_clocks_probe()
312 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
315 hws[IMX8MM_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); in imx8mm_clocks_probe()
316 hws[IMX8MM_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); in imx8mm_clocks_probe()
317 hws[IMX8MM_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); in imx8mm_clocks_probe()
318 hws[IMX8MM_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); in imx8mm_clocks_probe()
319 hws[IMX8MM_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); in imx8mm_clocks_probe()
320 hws[IMX8MM_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); in imx8mm_clocks_probe()
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| H A D | clk-imx6ul.c | 72 static struct clk_hw **hws; variable
133 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6ul_clocks_init()
139 hws = clk_hw_data->hws; in imx6ul_clocks_init()
141 hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6ul_clocks_init()
143 hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx6ul_clocks_init()
144 hws[IMX6UL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); in imx6ul_clocks_init()
147 hws[IMX6UL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); in imx6ul_clocks_init()
148 hws[IMX6UL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); in imx6ul_clocks_init()
155 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
156 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
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| H A D | clk-imx8mn.c | 317 static struct clk_hw **hws; variable
326 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, in imx8mn_clocks_probe()
332 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
335 hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); in imx8mn_clocks_probe()
336 hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); in imx8mn_clocks_probe()
337 hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); in imx8mn_clocks_probe()
338 hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); in imx8mn_clocks_probe()
339 hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); in imx8mn_clocks_probe()
340 hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); in imx8mn_clocks_probe()
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| H A D | clk-imx6sl.c | 100 static struct clk_hw **hws; variable
188 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sl_clocks_init()
194 hws = clk_hw_data->hws; in imx6sl_clocks_init()
196 hws[IMX6SL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sl_clocks_init()
197 hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0); in imx6sl_clocks_init()
198 hws[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock_hw("osc", 0); in imx6sl_clocks_init()
200 hws[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock_hw("anaclk1", 0); in imx6sl_clocks_init()
208 …hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
209 …hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
210 …hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
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| H A D | clk-imx6sll.c | 56 static struct clk_hw **hws; variable
84 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
92 hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sll_clocks_init()
94 hws[IMX6SLL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); in imx6sll_clocks_init()
95 hws[IMX6SLL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); in imx6sll_clocks_init()
98 hws[IMX6SLL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); in imx6sll_clocks_init()
99 hws[IMX6SLL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); in imx6sll_clocks_init()
115 …hws[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_sr… in imx6sll_clocks_init()
116 …hws[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_sr… in imx6sll_clocks_init()
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| H A D | clk-imx6q.c | 93 static struct clk_hw **hws; variable
275 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
276 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); in mmdc_ch1_disable()
350 (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in init_ldb_clks()
351 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { in init_ldb_clks()
403 if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in disable_anatop_clocks()
404 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) in disable_anatop_clocks()
442 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6q_clocks_init()
448 hws = clk_hw_data->hws; in imx6q_clocks_init()
450 hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6q_clocks_init()
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| H A D | clk-imx7ulp.c | 49 struct clk_hw **hws; in imx7ulp_clk_scg1_init() local
52 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END), in imx7ulp_clk_scg1_init()
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
60 hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7ulp_clk_scg1_init()
62 hws[IMX7ULP_CLK_ROSC] = imx_get_clk_hw_by_name(np, "rosc"); in imx7ulp_clk_scg1_init()
63 hws[IMX7ULP_CLK_SOSC] = imx_get_clk_hw_by_name(np, "sosc"); in imx7ulp_clk_scg1_init()
64 hws[IMX7ULP_CLK_SIRC] = imx_get_clk_hw_by_name(np, "sirc"); in imx7ulp_clk_scg1_init()
65 hws[IMX7ULP_CLK_FIRC] = imx_get_clk_hw_by_name(np, "firc"); in imx7ulp_clk_scg1_init()
66 hws[IMX7ULP_CLK_UPLL] = imx_get_clk_hw_by_name(np, "upll"); in imx7ulp_clk_scg1_init()
73 …hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
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| H A D | clk-imxrt1050.c | 33 static struct clk_hw **hws; variable
45 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, in imxrt1050_clocks_probe()
51 hws = clk_hw_data->hws; in imxrt1050_clocks_probe()
53 hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc"); in imxrt1050_clocks_probe()
64 hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL); in imxrt1050_clocks_probe()
66 hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel", in imxrt1050_clocks_probe()
68 hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel", in imxrt1050_clocks_probe()
70 hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel", in imxrt1050_clocks_probe()
72 hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel", in imxrt1050_clocks_probe()
75 hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1_arm", in imxrt1050_clocks_probe()
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| /openbmc/linux/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1.c | 464 static struct clk_hw **hws; in ma35d1_clocks_probe() local
470 struct_size(ma35d1_hw_data, hws, CLK_MAX_IDX), in ma35d1_clocks_probe()
476 hws = ma35d1_hw_data->hws; in ma35d1_clocks_probe()
488 hws[HXT] = ma35d1_clk_fixed("hxt", 24000000); in ma35d1_clocks_probe()
489 hws[HXT_GATE] = ma35d1_clk_gate(dev, "hxt_gate", "hxt", in ma35d1_clocks_probe()
491 hws[LXT] = ma35d1_clk_fixed("lxt", 32768); in ma35d1_clocks_probe()
492 hws[LXT_GATE] = ma35d1_clk_gate(dev, "lxt_gate", "lxt", in ma35d1_clocks_probe()
494 hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000); in ma35d1_clocks_probe()
495 hws[HIRC_GATE] = ma35d1_clk_gate(dev, "hirc_gate", "hirc", in ma35d1_clocks_probe()
497 hws[LIRC] = ma35d1_clk_fixed("lirc", 32000); in ma35d1_clocks_probe()
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| /openbmc/u-boot/drivers/hwspinlock/ |
| H A D | hwspinlock-uclass.c | 18 static int hwspinlock_of_xlate_default(struct hwspinlock *hws, in hwspinlock_of_xlate_default() argument
27 hws->id = args->args[0]; in hwspinlock_of_xlate_default()
29 hws->id = 0; in hwspinlock_of_xlate_default()
35 struct hwspinlock *hws) in hwspinlock_get_by_index() argument
42 assert(hws); in hwspinlock_get_by_index()
43 hws->dev = NULL; in hwspinlock_get_by_index()
62 hws->dev = dev_hws; in hwspinlock_get_by_index()
67 ret = ops->of_xlate(hws, &args); in hwspinlock_get_by_index()
69 ret = hwspinlock_of_xlate_default(hws, &args); in hwspinlock_get_by_index()
76 int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout) in hwspinlock_lock_timeout() argument
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-loongson2.c | 211 struct clk_hw **hws; in loongson2_clk_probe() local
220 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END), in loongson2_clk_probe()
226 hws = clk_hw_data->hws; in loongson2_clk_probe()
228 hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll", in loongson2_clk_probe()
232 hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll", in loongson2_clk_probe()
236 hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll", in loongson2_clk_probe()
240 hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll", in loongson2_clk_probe()
244 hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll", in loongson2_clk_probe()
248 hws[LOONGSON2_BOOT_CLK] = loongson2_clk_register(dev, "boot", in loongson2_clk_probe()
252 hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node", in loongson2_clk_probe()
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| H A D | clk-clps711x.c | 56 clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws, in clps711x_clk_init_dt()
108 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] = in clps711x_clk_init_dt()
110 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] = in clps711x_clk_init_dt()
112 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] = in clps711x_clk_init_dt()
114 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] = in clps711x_clk_init_dt()
116 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] = in clps711x_clk_init_dt()
118 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] = in clps711x_clk_init_dt()
122 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] = in clps711x_clk_init_dt()
126 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] = in clps711x_clk_init_dt()
128 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] = in clps711x_clk_init_dt()
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| H A D | clk-sp7021.c | 603 struct clk_hw **hws; in sp7021_clk_probe() local
620 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_MAX), in sp7021_clk_probe()
626 hws = clk_data->hws; in sp7021_clk_probe()
630 hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL, in sp7021_clk_probe()
632 if (IS_ERR(hws[PLL_A])) in sp7021_clk_probe()
633 return PTR_ERR(hws[PLL_A]); in sp7021_clk_probe()
635 hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL, in sp7021_clk_probe()
637 if (IS_ERR(hws[PLL_E])) in sp7021_clk_probe()
638 return PTR_ERR(hws[PLL_E]); in sp7021_clk_probe()
639 pd_e.hw = hws[PLL_E]; in sp7021_clk_probe()
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| /openbmc/linux/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 50 .hws = {
156 u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC0] = in u8500_clk_init()
160 u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC1] = in u8500_clk_init()
164 u8500_prcmu_hw_clks.hws[PRCMU_PLLDDR] = in u8500_clk_init()
202 u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] = in u8500_clk_init()
206 u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] = in u8500_clk_init()
209 u8500_prcmu_hw_clks.hws[PRCMU_UARTCLK] = in u8500_clk_init()
211 u8500_prcmu_hw_clks.hws[PRCMU_MSP02CLK] = in u8500_clk_init()
213 u8500_prcmu_hw_clks.hws[PRCMU_MSP1CLK] = in u8500_clk_init()
215 u8500_prcmu_hw_clks.hws[PRCMU_I2CCLK] = in u8500_clk_init()
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| /openbmc/u-boot/test/dm/ |
| H A D | hwspinlock.c | 18 struct hwspinlock hws; in dm_test_hwspinlock_base() local
20 ut_assertok(uclass_get_device(UCLASS_HWSPINLOCK, 0, &hws.dev)); in dm_test_hwspinlock_base()
21 ut_assertnonnull(hws.dev); in dm_test_hwspinlock_base()
24 hws.id = 0; in dm_test_hwspinlock_base()
25 ut_assertok(hwspinlock_lock_timeout(&hws, 1)); in dm_test_hwspinlock_base()
28 ut_assertok(hwspinlock_unlock(&hws)); in dm_test_hwspinlock_base()
31 ut_assertok(hwspinlock_lock_timeout(&hws, 1)); in dm_test_hwspinlock_base()
32 ut_assertok(!hwspinlock_lock_timeout(&hws, 1)); in dm_test_hwspinlock_base()
34 ut_assertok(hwspinlock_unlock(&hws)); in dm_test_hwspinlock_base()
35 ut_assertok(!hwspinlock_unlock(&hws)); in dm_test_hwspinlock_base()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_hwseq.c | 32 hws->ctx
34 hws->regs->reg
38 hws->shifts->field_name, hws->masks->field_name
40 void dce_enable_fe_clock(struct dce_hwseq *hws, in dce_enable_fe_clock() argument
53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock() local
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
80 if (hws->wa.blnd_crtc_trigger) { in dce_pipe_control_lock()
97 void dce_set_blender_mode(struct dce_hwseq *hws, in dce_set_blender_mode() argument
129 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
138 static void dce_disable_sram_shut_down(struct dce_hwseq *hws) in dce_disable_sram_shut_down() argument
[all …]
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| /openbmc/linux/drivers/clk/x86/ |
| H A D | clk-fch.c | 38 static struct clk_hw *hws[ST_MAX_CLKS]; variable
61 hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
63 hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", in fch_clk_probe()
66 hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux", in fch_clk_probe()
71 clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); in fch_clk_probe()
73 hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
77 devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], in fch_clk_probe()
80 hws[CLK_48M_FIXED] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
83 hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
87 devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED], in fch_clk_probe()
[all …]
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| /openbmc/linux/drivers/isdn/hardware/mISDN/ |
| H A D | iohelper.h | 25 #define IOFUNC_IO(name, hws, ap) \ argument
27 struct hws *hw = p; \
31 struct hws *hw = p; \
35 struct hws *hw = p; \
39 struct hws *hw = p; \
43 #define IOFUNC_IND(name, hws, ap) \ argument
45 struct hws *hw = p; \
50 struct hws *hw = p; \
55 struct hws *hw = p; \
60 struct hws *hw = p; \
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_hwseq.c | 18 hws->ctx
20 hws->regs->reg
24 hws->shifts->field_name, hws->masks->field_name
27 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn303_dpp_pg_control() argument
32 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) in dcn303_hubp_pg_control() argument
37 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) in dcn303_dsc_pg_control() argument
42 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) in dcn303_enable_power_gating_plane() argument
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mtk.c | 47 clk_data->hws[i] = ERR_PTR(-ENOENT); in mtk_init_clk_data()
55 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, clk_num), in mtk_devm_alloc_clk_data()
70 clk_data = kzalloc(struct_size(clk_data, hws, clk_num), GFP_KERNEL); in mtk_alloc_clk_data()
98 if (!IS_ERR_OR_NULL(clk_data->hws[rc->id])) { in mtk_clk_register_fixed_clks()
112 clk_data->hws[rc->id] = hw; in mtk_clk_register_fixed_clks()
121 if (IS_ERR_OR_NULL(clk_data->hws[rc->id])) in mtk_clk_register_fixed_clks()
124 clk_hw_unregister_fixed_rate(clk_data->hws[rc->id]); in mtk_clk_register_fixed_clks()
125 clk_data->hws[rc->id] = ERR_PTR(-ENOENT); in mtk_clk_register_fixed_clks()
143 if (IS_ERR_OR_NULL(clk_data->hws[rc->id])) in mtk_clk_unregister_fixed_clks()
146 clk_hw_unregister_fixed_rate(clk_data->hws[rc->id]); in mtk_clk_unregister_fixed_clks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/i915/selftests/ |
| H A D | igt_spinner.c | 21 spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in igt_spinner_init()
22 if (IS_ERR(spin->hws)) { in igt_spinner_init()
23 err = PTR_ERR(spin->hws); in igt_spinner_init()
26 i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC); in igt_spinner_init()
37 i915_gem_object_put(spin->hws); in igt_spinner_init()
90 vaddr = igt_spinner_pin_obj(ce, ww, spin->hws, I915_MAP_WB, &spin->hws_vma); in igt_spinner_pin()
116 static u64 hws_address(const struct i915_vma *hws, in hws_address() argument
119 return i915_vma_offset(hws) + seqno_offset(rq->fence.context); in hws_address()
129 struct i915_vma *hws, *vma; in igt_spinner_create_request() local
145 hws = spin->hws_vma; in igt_spinner_create_request()
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