| /openbmc/u-boot/arch/riscv/lib/ |
| H A D | sifive_clint.c | 18 #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) argument
20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) argument
47 int riscv_set_timecmp(int hart, u64 cmp) in riscv_set_timecmp() argument
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
56 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
60 writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_send_ipi()
65 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
69 writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_clear_ipi()
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| H A D | bootm.c | 82 void (*kernel)(ulong hart, void *dtb); in boot_jump_linux()
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| /openbmc/linux/arch/riscv/kernel/ |
| H A D | cpu.c | 29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
33 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
34 if (*hart == ~0UL) { in riscv_of_processor_hartid()
39 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
49 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument
58 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
59 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
65 pr_info("CPU with hartid=%lu is not available\n", *hart); in riscv_early_of_processor_hartid()
73 pr_warn("CPU with hartid=%lu does not support rv32i", *hart); in riscv_early_of_processor_hartid()
78 pr_warn("CPU with hartid=%lu does not support rv64i", *hart); in riscv_early_of_processor_hartid()
[all …]
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| H A D | smpboot.c | 82 unsigned long hart; in acpi_parse_rintc() local
99 hart = processor->hart_id; in acpi_parse_rintc()
100 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
105 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
117 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
146 unsigned long hart; in of_parse_and_init_cpus() local
154 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
158 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
166 cpuid, hart); in of_parse_and_init_cpus()
170 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
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| /openbmc/qemu/target/riscv/ |
| H A D | trace-events | 2 …ol async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d…
5 pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" P…
6 pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%"…
7 pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%…
8 pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write add…
10 mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
11 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
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| /openbmc/linux/tools/perf/pmu-events/arch/riscv/ |
| H A D | mapfile.csv | 6 # MARCHID base microarchitecture of the hart
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| /openbmc/linux/arch/riscv/kvm/ |
| H A D | aia_device.c | 240 u32 hart = 0, group = 0; in aia_imsic_hart_index() local
243 hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) & in aia_imsic_hart_index()
249 return (group << aia->nr_hart_bits) | hart; in aia_imsic_hart_index()
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| /openbmc/linux/Documentation/riscv/ |
| H A D | boot.rst | 68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
72 - ``Ordered booting``: the firmware releases only one hart that will execute the
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| /openbmc/qemu/docs/system/riscv/ |
| H A D | microchip-icicle-kit.rst | 149 .. _HSS: https://github.com/polarfire-soc/hart-software-services
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| /openbmc/linux/arch/riscv/ |
| H A D | Kconfig | 669 Since spinwait is incompatible with sparse hart IDs, it requires
670 NR_CPUS be large enough to contain the physical hart ID of the first
671 hart to enter Linux.
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| /openbmc/qemu/hw/riscv/ |
| H A D | virt.c | 718 RISCVCPU hart = s->soc[0].harts[0]; in create_fdt_pmu() local
722 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); in create_fdt_pmu()
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| /openbmc/linux/drivers/clocksource/ |
| H A D | Kconfig | 641 This enables the per-hart timer built into all RISC-V systems, which
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