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/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c83 unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */ member
95 unsigned int fbdiv; member
102 u32 fbdiv; member
107 char fbdiv; member
118 .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
125 .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
130 .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
149 u32 fbdiv; member
163 .fbdiv = 125,
169 .fbdiv = 125,
[all …]
/openbmc/linux/drivers/clk/zynqmp/
H A Dpll.c104 u32 fbdiv; in zynqmp_pll_round_rate() local
117 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynqmp_pll_round_rate()
118 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { in zynqmp_pll_round_rate()
119 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); in zynqmp_pll_round_rate()
120 rate = *prate * fbdiv; in zynqmp_pll_round_rate()
139 u32 fbdiv, data; in zynqmp_pll_recalc_rate() local
145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); in zynqmp_pll_recalc_rate()
156 rate = parent_rate * fbdiv; in zynqmp_pll_recalc_rate()
183 u32 fbdiv; in zynqmp_pll_set_rate() local
209 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); in zynqmp_pll_set_rate()
[all …]
/openbmc/linux/drivers/clk/zynq/
H A Dpll.c54 u32 fbdiv; in zynq_pll_round_rate() local
56 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynq_pll_round_rate()
57 if (fbdiv < PLL_FBDIV_MIN) in zynq_pll_round_rate()
58 fbdiv = PLL_FBDIV_MIN; in zynq_pll_round_rate()
59 else if (fbdiv > PLL_FBDIV_MAX) in zynq_pll_round_rate()
60 fbdiv = PLL_FBDIV_MAX; in zynq_pll_round_rate()
62 return *prate * fbdiv; in zynq_pll_round_rate()
75 u32 fbdiv; in zynq_pll_recalc_rate() local
81 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
84 return parent_rate * fbdiv; in zynq_pll_recalc_rate()
/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c231 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
267 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_configure_for_rate()
279 f >>= (fbdiv - 1); in wrpll_configure_for_rate()
282 vco_pre = fbdiv * post_divr_freq; in wrpll_configure_for_rate()
337 u8 fbdiv; in wrpll_calc_output_rate() local
345 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_calc_output_rate()
346 n = parent_rate * fbdiv * (c->divf + 1); in wrpll_calc_output_rate()
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
61 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
78 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config() local
114 fbdiv = vco_khz / fref_khz; in pll_para_config()
115 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) in pll_para_config()
117 diff_khz = vco_khz - fbdiv * fref_khz; in pll_para_config()
118 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { in pll_para_config()
119 fbdiv++; in pll_para_config()
[all …]
H A Dclk_rk3399.c34 u32 fbdiv; member
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
322 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
326 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
340 div->fbdiv << PLL_FBDIV_SHIFT); in rkclk_set_pll()
359 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
395 fbdiv = vco_khz / fref_khz; in pll_para_config()
396 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) in pll_para_config()
398 diff_khz = vco_khz - fbdiv * fref_khz; in pll_para_config()
[all …]
H A Dclk_rk322x.c30 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
64 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
200 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
H A Dclk_rk3036.c33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
66 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
199 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_rk3328.c22 u32 fbdiv; member
34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
241 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
264 (div->fbdiv << PLL_FBDIV_SHIFT) | in rkclk_set_pll()
H A Dclk_rv1108.c33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
131 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c247 u8 fbdiv, divq, best_r, r; in analogbits_wrpll_configure_for_rate() local
296 fbdiv = __wrpll_calc_fbdiv(c); in analogbits_wrpll_configure_for_rate()
309 f >>= (fbdiv - 1); in analogbits_wrpll_configure_for_rate()
312 vco_pre = fbdiv * post_divr_freq; in analogbits_wrpll_configure_for_rate()
361 u8 fbdiv; in analogbits_wrpll_calc_output_rate() local
367 fbdiv = __wrpll_calc_fbdiv(c); in analogbits_wrpll_calc_output_rate()
368 n = parent_rate * fbdiv * (c->divf + 1); in analogbits_wrpll_calc_output_rate()
/openbmc/linux/drivers/clk/pistachio/
H A Dclk-pll.c211 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
230 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT); in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
277 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_frac_recalc_rate()
289 rate *= (fbdiv << 24) + frac; in pll_gf40lp_frac_recalc_rate()
291 rate *= (fbdiv << 24); in pll_gf40lp_frac_recalc_rate()
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
398 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
418 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_laint_recalc_rate()
[all …]
/openbmc/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c27 unsigned int fbdiv; member
102 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
105 fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG)); in i2s_pll_recalc_rate()
108 return ((parent_rate / idiv) * fbdiv) / odiv; in i2s_pll_recalc_rate()
145 i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv); in i2s_pll_set_rate()
H A Dpll_clock.c69 u32 fbdiv; member
139 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
143 fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV)); in axs10x_pll_recalc_rate()
146 rate = (u64)parent_rate * fbdiv; in axs10x_pll_recalc_rate()
185 axs10x_encode_div(pll_cfg[i].fbdiv, 0)); in axs10x_pll_set_rate()
/openbmc/linux/drivers/clk/mmp/
H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
59 fbdiv = (val >> pll->shift) & 0x1ff; in mmp_clk_pll_recalc_rate()
62 fbdiv = 2; in mmp_clk_pll_recalc_rate()
74 rate *= 2 * fbdiv; in mmp_clk_pll_recalc_rate()
88 rate *= fbdiv + 2; in mmp_clk_pll_recalc_rate()
/openbmc/u-boot/drivers/video/rockchip/
H A Drk_mipi.c202 u64 fbdiv; in rk_mipi_phy_enable() local
280 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
281 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
285 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
290 test_data[0] = (fbdiv - 1) & 0x1f; in rk_mipi_phy_enable()
292 test_data[0] = (fbdiv - 1) >> 5 | 0x80; in rk_mipi_phy_enable()
/openbmc/linux/drivers/clk/berlin/
H A Dberlin2-pll.c46 u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; in berlin2_pll_recalc_rate() local
50 fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; in berlin2_pll_recalc_rate()
66 rate *= fbdiv * map->mult; in berlin2_pll_recalc_rate()
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-pll.c145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
172 rate64 *= cur.fbdiv; in rockchip_rk3036_pll_recalc_rate()
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
324 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
625 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) in rockchip_rk3399_pll_get_params()
654 rate64 *= cur.fbdiv; in rockchip_rk3399_pll_recalc_rate()
683 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-sp7021.c405 u32 fbdiv; in sp_pll_calc_div() local
408 fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate); in sp_pll_calc_div()
409 if (fbdiv > max) in sp_pll_calc_div()
410 fbdiv = max; in sp_pll_calc_div()
412 return fbdiv; in sp_pll_calc_div()
473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; in sp_pll_recalc_rate() local
475 ret = clk->brate * fbdiv; in sp_pll_recalc_rate()
497 u32 fbdiv = sp_pll_calc_div(clk, rate); in sp_pll_set_rate() local
501 reg |= ((fbdiv - 1) << clk->div_shift) & mask; in sp_pll_set_rate()
H A Dclk-hsdk-pll.c49 u32 fbdiv; member
142 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; in hsdk_pll_set_cfg()
172 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
190 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); in hsdk_pll_recalc_rate()
194 rate = (u64)parent_rate * fbdiv; in hsdk_pll_recalc_rate()
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
57 fbdiv = ((control >> 4) & 0xfff) + 3; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi.c254 u16 fbdiv; member
269 u16 fbdiv; member
797 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3228_clk_set_rate()
800 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_clk_set_rate()
958 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); in inno_hdmi_phy_rk3328_clk_set_rate()
959 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
1073 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
1074 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
1181 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_power_on()
1183 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
[all …]
H A Dphy-rockchip-inno-dsidphy.c221 u16 fbdiv; member
359 inno->pll.fbdiv = best_fbdiv; in inno_dsidphy_pll_calc_rate()
387 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
389 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
530 u16 fbdiv = 28; in inno_dsidphy_lvds_mode_enable() local
545 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv)); in inno_dsidphy_lvds_mode_enable()
547 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); in inno_dsidphy_lvds_mode_enable()
/openbmc/u-boot/drivers/clk/
H A Dclk-hsdk-cgu.c185 u32 fbdiv; member
350 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; in hsdk_pll_set_cfg()
373 u32 idiv, fbdiv, odiv; in pll_get() local
391 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); in pll_get()
395 rate = (u64)PARENT_RATE * fbdiv; in pll_get()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv740_dpm.c132 u32 fbdiv; in rv740_populate_sclk_value() local
144 fbdiv = (u32) tmp; in rv740_populate_sclk_value()
154 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv740_populate_sclk_value()
164 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in rv740_populate_sclk_value()

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