xref: /openbmc/u-boot/drivers/clk/sifive/wrpll-cln28hpc.c (revision 783e66816d101f970b185083377846059d4d577d)
1*c40b6df8SAnup Patel // SPDX-License-Identifier: GPL-2.0
2*c40b6df8SAnup Patel /*
3*c40b6df8SAnup Patel  * Copyright (c) 2019 Western Digital Corporation or its affiliates.
4*c40b6df8SAnup Patel  *
5*c40b6df8SAnup Patel  * Copyright (C) 2018 SiFive, Inc.
6*c40b6df8SAnup Patel  * Wesley Terpstra
7*c40b6df8SAnup Patel  * Paul Walmsley
8*c40b6df8SAnup Patel  *
9*c40b6df8SAnup Patel  * This program is free software; you can redistribute it and/or modify
10*c40b6df8SAnup Patel  * it under the terms of the GNU General Public License version 2 as
11*c40b6df8SAnup Patel  * published by the Free Software Foundation.
12*c40b6df8SAnup Patel  *
13*c40b6df8SAnup Patel  * This program is distributed in the hope that it will be useful,
14*c40b6df8SAnup Patel  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15*c40b6df8SAnup Patel  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16*c40b6df8SAnup Patel  * GNU General Public License for more details.
17*c40b6df8SAnup Patel  *
18*c40b6df8SAnup Patel  * This library supports configuration parsing and reprogramming of
19*c40b6df8SAnup Patel  * the CLN28HPC variant of the Analog Bits Wide Range PLL.  The
20*c40b6df8SAnup Patel  * intention is for this library to be reusable for any device that
21*c40b6df8SAnup Patel  * integrates this PLL; thus the register structure and programming
22*c40b6df8SAnup Patel  * details are expected to be provided by a separate IP block driver.
23*c40b6df8SAnup Patel  *
24*c40b6df8SAnup Patel  * The bulk of this code is primarily useful for clock configurations
25*c40b6df8SAnup Patel  * that must operate at arbitrary rates, as opposed to clock configurations
26*c40b6df8SAnup Patel  * that are restricted by software or manufacturer guidance to a small,
27*c40b6df8SAnup Patel  * pre-determined set of performance points.
28*c40b6df8SAnup Patel  *
29*c40b6df8SAnup Patel  * References:
30*c40b6df8SAnup Patel  * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
31*c40b6df8SAnup Patel  * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
32*c40b6df8SAnup Patel  */
33*c40b6df8SAnup Patel 
34*c40b6df8SAnup Patel #include <linux/bug.h>
35*c40b6df8SAnup Patel #include <linux/err.h>
36*c40b6df8SAnup Patel #include <linux/log2.h>
37*c40b6df8SAnup Patel #include <linux/math64.h>
38*c40b6df8SAnup Patel 
39*c40b6df8SAnup Patel #include "analogbits-wrpll-cln28hpc.h"
40*c40b6df8SAnup Patel 
41*c40b6df8SAnup Patel /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
42*c40b6df8SAnup Patel #define MIN_INPUT_FREQ			7000000
43*c40b6df8SAnup Patel 
44*c40b6df8SAnup Patel /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
45*c40b6df8SAnup Patel #define MAX_INPUT_FREQ			600000000
46*c40b6df8SAnup Patel 
47*c40b6df8SAnup Patel /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
48*c40b6df8SAnup Patel #define MIN_POST_DIVR_FREQ		7000000
49*c40b6df8SAnup Patel 
50*c40b6df8SAnup Patel /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
51*c40b6df8SAnup Patel #define MAX_POST_DIVR_FREQ		200000000
52*c40b6df8SAnup Patel 
53*c40b6df8SAnup Patel /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
54*c40b6df8SAnup Patel #define MIN_VCO_FREQ			2400000000UL
55*c40b6df8SAnup Patel 
56*c40b6df8SAnup Patel /* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
57*c40b6df8SAnup Patel #define MAX_VCO_FREQ			4800000000ULL
58*c40b6df8SAnup Patel 
59*c40b6df8SAnup Patel /* MAX_DIVQ_DIVISOR: maximum output divisor.  Selected by DIVQ = 6 */
60*c40b6df8SAnup Patel #define MAX_DIVQ_DIVISOR		64
61*c40b6df8SAnup Patel 
62*c40b6df8SAnup Patel /* MAX_DIVR_DIVISOR: maximum reference divisor.  Selected by DIVR = 63 */
63*c40b6df8SAnup Patel #define MAX_DIVR_DIVISOR		64
64*c40b6df8SAnup Patel 
65*c40b6df8SAnup Patel /* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */
66*c40b6df8SAnup Patel #define MAX_LOCK_US			70
67*c40b6df8SAnup Patel 
68*c40b6df8SAnup Patel /*
69*c40b6df8SAnup Patel  * ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding
70*c40b6df8SAnup Patel  *              algorithm
71*c40b6df8SAnup Patel  */
72*c40b6df8SAnup Patel #define ROUND_SHIFT			20
73*c40b6df8SAnup Patel 
74*c40b6df8SAnup Patel /*
75*c40b6df8SAnup Patel  * Private functions
76*c40b6df8SAnup Patel  */
77*c40b6df8SAnup Patel 
78*c40b6df8SAnup Patel /**
79*c40b6df8SAnup Patel  * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
80*c40b6df8SAnup Patel  * @post_divr_freq: input clock rate after the R divider
81*c40b6df8SAnup Patel  *
82*c40b6df8SAnup Patel  * Select the value to be presented to the PLL RANGE input signals, based
83*c40b6df8SAnup Patel  * on the input clock frequency after the post-R-divider @post_divr_freq.
84*c40b6df8SAnup Patel  * This code follows the recommendations in the PLL datasheet for filter
85*c40b6df8SAnup Patel  * range selection.
86*c40b6df8SAnup Patel  *
87*c40b6df8SAnup Patel  * Return: The RANGE value to be presented to the PLL configuration inputs,
88*c40b6df8SAnup Patel  *         or -1 upon error.
89*c40b6df8SAnup Patel  */
__wrpll_calc_filter_range(unsigned long post_divr_freq)90*c40b6df8SAnup Patel static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
91*c40b6df8SAnup Patel {
92*c40b6df8SAnup Patel 	u8 range;
93*c40b6df8SAnup Patel 
94*c40b6df8SAnup Patel 	if (post_divr_freq < MIN_POST_DIVR_FREQ ||
95*c40b6df8SAnup Patel 	    post_divr_freq > MAX_POST_DIVR_FREQ) {
96*c40b6df8SAnup Patel 		WARN(1, "%s: post-divider reference freq out of range: %lu",
97*c40b6df8SAnup Patel 		     __func__, post_divr_freq);
98*c40b6df8SAnup Patel 		return -1;
99*c40b6df8SAnup Patel 	}
100*c40b6df8SAnup Patel 
101*c40b6df8SAnup Patel 	if (post_divr_freq < 11000000)
102*c40b6df8SAnup Patel 		range = 1;
103*c40b6df8SAnup Patel 	else if (post_divr_freq < 18000000)
104*c40b6df8SAnup Patel 		range = 2;
105*c40b6df8SAnup Patel 	else if (post_divr_freq < 30000000)
106*c40b6df8SAnup Patel 		range = 3;
107*c40b6df8SAnup Patel 	else if (post_divr_freq < 50000000)
108*c40b6df8SAnup Patel 		range = 4;
109*c40b6df8SAnup Patel 	else if (post_divr_freq < 80000000)
110*c40b6df8SAnup Patel 		range = 5;
111*c40b6df8SAnup Patel 	else if (post_divr_freq < 130000000)
112*c40b6df8SAnup Patel 		range = 6;
113*c40b6df8SAnup Patel 	else
114*c40b6df8SAnup Patel 		range = 7;
115*c40b6df8SAnup Patel 
116*c40b6df8SAnup Patel 	return range;
117*c40b6df8SAnup Patel }
118*c40b6df8SAnup Patel 
119*c40b6df8SAnup Patel /**
120*c40b6df8SAnup Patel  * __wrpll_calc_fbdiv() - return feedback fixed divide value
121*c40b6df8SAnup Patel  * @c: ptr to a struct analogbits_wrpll_cfg record to read from
122*c40b6df8SAnup Patel  *
123*c40b6df8SAnup Patel  * The internal feedback path includes a fixed by-two divider; the
124*c40b6df8SAnup Patel  * external feedback path does not.  Return the appropriate divider
125*c40b6df8SAnup Patel  * value (2 or 1) depending on whether internal or external feedback
126*c40b6df8SAnup Patel  * is enabled.  This code doesn't test for invalid configurations
127*c40b6df8SAnup Patel  * (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies
128*c40b6df8SAnup Patel  * on the caller to do so.
129*c40b6df8SAnup Patel  *
130*c40b6df8SAnup Patel  * Context: Any context.  Caller must protect the memory pointed to by
131*c40b6df8SAnup Patel  *          @c from simultaneous modification.
132*c40b6df8SAnup Patel  *
133*c40b6df8SAnup Patel  * Return: 2 if internal feedback is enabled or 1 if external feedback
134*c40b6df8SAnup Patel  *         is enabled.
135*c40b6df8SAnup Patel  */
__wrpll_calc_fbdiv(struct analogbits_wrpll_cfg * c)136*c40b6df8SAnup Patel static u8 __wrpll_calc_fbdiv(struct analogbits_wrpll_cfg *c)
137*c40b6df8SAnup Patel {
138*c40b6df8SAnup Patel 	return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
139*c40b6df8SAnup Patel }
140*c40b6df8SAnup Patel 
141*c40b6df8SAnup Patel /**
142*c40b6df8SAnup Patel  * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
143*c40b6df8SAnup Patel  * @target_rate: target PLL output clock rate
144*c40b6df8SAnup Patel  * @vco_rate: pointer to a u64 to store the computed VCO rate into
145*c40b6df8SAnup Patel  *
146*c40b6df8SAnup Patel  * Determine a reasonable value for the PLL Q post-divider, based on the
147*c40b6df8SAnup Patel  * target output rate @target_rate for the PLL.  Along with returning the
148*c40b6df8SAnup Patel  * computed Q divider value as the return value, this function stores the
149*c40b6df8SAnup Patel  * desired target VCO rate into the variable pointed to by @vco_rate.
150*c40b6df8SAnup Patel  *
151*c40b6df8SAnup Patel  * Context: Any context.  Caller must protect the memory pointed to by
152*c40b6df8SAnup Patel  *          @vco_rate from simultaneous access or modification.
153*c40b6df8SAnup Patel  *
154*c40b6df8SAnup Patel  * Return: a positive integer DIVQ value to be programmed into the hardware
155*c40b6df8SAnup Patel  *         upon success, or 0 upon error (since 0 is an invalid DIVQ value)
156*c40b6df8SAnup Patel  */
__wrpll_calc_divq(u32 target_rate,u64 * vco_rate)157*c40b6df8SAnup Patel static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
158*c40b6df8SAnup Patel {
159*c40b6df8SAnup Patel 	u64 s;
160*c40b6df8SAnup Patel 	u8 divq = 0;
161*c40b6df8SAnup Patel 
162*c40b6df8SAnup Patel 	if (!vco_rate) {
163*c40b6df8SAnup Patel 		WARN_ON(1);
164*c40b6df8SAnup Patel 		goto wcd_out;
165*c40b6df8SAnup Patel 	}
166*c40b6df8SAnup Patel 
167*c40b6df8SAnup Patel 	s = div_u64(MAX_VCO_FREQ, target_rate);
168*c40b6df8SAnup Patel 	if (s <= 1) {
169*c40b6df8SAnup Patel 		divq = 1;
170*c40b6df8SAnup Patel 		*vco_rate = MAX_VCO_FREQ;
171*c40b6df8SAnup Patel 	} else if (s > MAX_DIVQ_DIVISOR) {
172*c40b6df8SAnup Patel 		divq = ilog2(MAX_DIVQ_DIVISOR);
173*c40b6df8SAnup Patel 		*vco_rate = MIN_VCO_FREQ;
174*c40b6df8SAnup Patel 	} else {
175*c40b6df8SAnup Patel 		divq = ilog2(s);
176*c40b6df8SAnup Patel 		*vco_rate = target_rate << divq;
177*c40b6df8SAnup Patel 	}
178*c40b6df8SAnup Patel 
179*c40b6df8SAnup Patel wcd_out:
180*c40b6df8SAnup Patel 	return divq;
181*c40b6df8SAnup Patel }
182*c40b6df8SAnup Patel 
183*c40b6df8SAnup Patel /**
184*c40b6df8SAnup Patel  * __wrpll_update_parent_rate() - update PLL data when parent rate changes
185*c40b6df8SAnup Patel  * @c: ptr to a struct analogbits_wrpll_cfg record to write PLL data to
186*c40b6df8SAnup Patel  * @parent_rate: PLL input refclk rate (pre-R-divider)
187*c40b6df8SAnup Patel  *
188*c40b6df8SAnup Patel  * Pre-compute some data used by the PLL configuration algorithm when
189*c40b6df8SAnup Patel  * the PLL's reference clock rate changes.  The intention is to avoid
190*c40b6df8SAnup Patel  * computation when the parent rate remains constant - expected to be
191*c40b6df8SAnup Patel  * the common case.
192*c40b6df8SAnup Patel  *
193*c40b6df8SAnup Patel  * Returns: 0 upon success or -1 if the reference clock rate is out of range.
194*c40b6df8SAnup Patel  */
__wrpll_update_parent_rate(struct analogbits_wrpll_cfg * c,unsigned long parent_rate)195*c40b6df8SAnup Patel static int __wrpll_update_parent_rate(struct analogbits_wrpll_cfg *c,
196*c40b6df8SAnup Patel 				      unsigned long parent_rate)
197*c40b6df8SAnup Patel {
198*c40b6df8SAnup Patel 	u8 max_r_for_parent;
199*c40b6df8SAnup Patel 
200*c40b6df8SAnup Patel 	if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
201*c40b6df8SAnup Patel 		return -1;
202*c40b6df8SAnup Patel 
203*c40b6df8SAnup Patel 	c->_parent_rate = parent_rate;
204*c40b6df8SAnup Patel 	max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
205*c40b6df8SAnup Patel 	c->_max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
206*c40b6df8SAnup Patel 
207*c40b6df8SAnup Patel 	/* Round up */
208*c40b6df8SAnup Patel 	c->_init_r = div_u64(parent_rate + MAX_POST_DIVR_FREQ - 1,
209*c40b6df8SAnup Patel 			     MAX_POST_DIVR_FREQ);
210*c40b6df8SAnup Patel 
211*c40b6df8SAnup Patel 	return 0;
212*c40b6df8SAnup Patel }
213*c40b6df8SAnup Patel 
214*c40b6df8SAnup Patel /*
215*c40b6df8SAnup Patel  * Public functions
216*c40b6df8SAnup Patel  */
217*c40b6df8SAnup Patel 
218*c40b6df8SAnup Patel /**
219*c40b6df8SAnup Patel  * analogbits_wrpll_configure() - compute PLL configuration for a target rate
220*c40b6df8SAnup Patel  * @c: ptr to a struct analogbits_wrpll_cfg record to write into
221*c40b6df8SAnup Patel  * @target_rate: target PLL output clock rate (post-Q-divider)
222*c40b6df8SAnup Patel  * @parent_rate: PLL input refclk rate (pre-R-divider)
223*c40b6df8SAnup Patel  *
224*c40b6df8SAnup Patel  * Given a pointer to a PLL context @c, a desired PLL target output
225*c40b6df8SAnup Patel  * rate @target_rate, and a reference clock input rate @parent_rate,
226*c40b6df8SAnup Patel  * compute the appropriate PLL signal configuration values.  PLL
227*c40b6df8SAnup Patel  * reprogramming is not glitchless, so the caller should switch any
228*c40b6df8SAnup Patel  * downstream logic to a different clock source or clock-gate it
229*c40b6df8SAnup Patel  * before presenting these values to the PLL configuration signals.
230*c40b6df8SAnup Patel  *
231*c40b6df8SAnup Patel  * The caller must pass this function a pre-initialized struct
232*c40b6df8SAnup Patel  * analogbits_wrpll_cfg record: either initialized to zero (with the
233*c40b6df8SAnup Patel  * exception of the .name and .flags fields) or read from the PLL.
234*c40b6df8SAnup Patel  *
235*c40b6df8SAnup Patel  * Context: Any context.  Caller must protect the memory pointed to by @c
236*c40b6df8SAnup Patel  *          from simultaneous access or modification.
237*c40b6df8SAnup Patel  *
238*c40b6df8SAnup Patel  * Return: 0 upon success; anything else upon failure.
239*c40b6df8SAnup Patel  */
analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg * c,u32 target_rate,unsigned long parent_rate)240*c40b6df8SAnup Patel int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
241*c40b6df8SAnup Patel 					u32 target_rate,
242*c40b6df8SAnup Patel 					unsigned long parent_rate)
243*c40b6df8SAnup Patel {
244*c40b6df8SAnup Patel 	unsigned long ratio;
245*c40b6df8SAnup Patel 	u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
246*c40b6df8SAnup Patel 	u32 best_f, f, post_divr_freq, fbcfg;
247*c40b6df8SAnup Patel 	u8 fbdiv, divq, best_r, r;
248*c40b6df8SAnup Patel 
249*c40b6df8SAnup Patel 	if (!c)
250*c40b6df8SAnup Patel 		return -1;
251*c40b6df8SAnup Patel 
252*c40b6df8SAnup Patel 	if (c->flags == 0) {
253*c40b6df8SAnup Patel 		WARN(1, "%s called with uninitialized PLL config", __func__);
254*c40b6df8SAnup Patel 		return -1;
255*c40b6df8SAnup Patel 	}
256*c40b6df8SAnup Patel 
257*c40b6df8SAnup Patel 	fbcfg = WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK;
258*c40b6df8SAnup Patel 	if ((c->flags & fbcfg) == fbcfg) {
259*c40b6df8SAnup Patel 		WARN(1, "%s called with invalid PLL config", __func__);
260*c40b6df8SAnup Patel 		return -1;
261*c40b6df8SAnup Patel 	}
262*c40b6df8SAnup Patel 
263*c40b6df8SAnup Patel 	if (c->flags == WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
264*c40b6df8SAnup Patel 		WARN(1, "%s: external feedback mode not currently supported",
265*c40b6df8SAnup Patel 		     __func__);
266*c40b6df8SAnup Patel 		return -1;
267*c40b6df8SAnup Patel 	}
268*c40b6df8SAnup Patel 
269*c40b6df8SAnup Patel 	/* Initialize rounding data if it hasn't been initialized already */
270*c40b6df8SAnup Patel 	if (parent_rate != c->_parent_rate) {
271*c40b6df8SAnup Patel 		if (__wrpll_update_parent_rate(c, parent_rate)) {
272*c40b6df8SAnup Patel 			pr_err("%s: PLL input rate is out of range\n",
273*c40b6df8SAnup Patel 			       __func__);
274*c40b6df8SAnup Patel 			return -1;
275*c40b6df8SAnup Patel 		}
276*c40b6df8SAnup Patel 	}
277*c40b6df8SAnup Patel 
278*c40b6df8SAnup Patel 	c->flags &= ~WRPLL_FLAGS_RESET_MASK;
279*c40b6df8SAnup Patel 
280*c40b6df8SAnup Patel 	/* Put the PLL into bypass if the user requests the parent clock rate */
281*c40b6df8SAnup Patel 	if (target_rate == parent_rate) {
282*c40b6df8SAnup Patel 		c->flags |= WRPLL_FLAGS_BYPASS_MASK;
283*c40b6df8SAnup Patel 		return 0;
284*c40b6df8SAnup Patel 	}
285*c40b6df8SAnup Patel 	c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
286*c40b6df8SAnup Patel 
287*c40b6df8SAnup Patel 	/* Calculate the Q shift and target VCO rate */
288*c40b6df8SAnup Patel 	divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
289*c40b6df8SAnup Patel 	if (divq == 0)
290*c40b6df8SAnup Patel 		return -1;
291*c40b6df8SAnup Patel 	c->divq = divq;
292*c40b6df8SAnup Patel 
293*c40b6df8SAnup Patel 	/* Precalculate the pre-Q divider target ratio */
294*c40b6df8SAnup Patel 	ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
295*c40b6df8SAnup Patel 
296*c40b6df8SAnup Patel 	fbdiv = __wrpll_calc_fbdiv(c);
297*c40b6df8SAnup Patel 	best_r = 0;
298*c40b6df8SAnup Patel 	best_f = 0;
299*c40b6df8SAnup Patel 	best_delta = MAX_VCO_FREQ;
300*c40b6df8SAnup Patel 
301*c40b6df8SAnup Patel 	/*
302*c40b6df8SAnup Patel 	 * Consider all values for R which land within
303*c40b6df8SAnup Patel 	 * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
304*c40b6df8SAnup Patel 	 */
305*c40b6df8SAnup Patel 	for (r = c->_init_r; r <= c->_max_r; ++r) {
306*c40b6df8SAnup Patel 		/* What is the best F we can pick in this case? */
307*c40b6df8SAnup Patel 		f_pre_div = ratio * r;
308*c40b6df8SAnup Patel 		f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
309*c40b6df8SAnup Patel 		f >>= (fbdiv - 1);
310*c40b6df8SAnup Patel 
311*c40b6df8SAnup Patel 		post_divr_freq = div_u64(parent_rate, r);
312*c40b6df8SAnup Patel 		vco_pre = fbdiv * post_divr_freq;
313*c40b6df8SAnup Patel 		vco = vco_pre * f;
314*c40b6df8SAnup Patel 
315*c40b6df8SAnup Patel 		/* Ensure rounding didn't take us out of range */
316*c40b6df8SAnup Patel 		if (vco > target_vco_rate) {
317*c40b6df8SAnup Patel 			--f;
318*c40b6df8SAnup Patel 			vco = vco_pre * f;
319*c40b6df8SAnup Patel 		} else if (vco < MIN_VCO_FREQ) {
320*c40b6df8SAnup Patel 			++f;
321*c40b6df8SAnup Patel 			vco = vco_pre * f;
322*c40b6df8SAnup Patel 		}
323*c40b6df8SAnup Patel 
324*c40b6df8SAnup Patel 		delta = abs(target_rate - vco);
325*c40b6df8SAnup Patel 		if (delta < best_delta) {
326*c40b6df8SAnup Patel 			best_delta = delta;
327*c40b6df8SAnup Patel 			best_r = r;
328*c40b6df8SAnup Patel 			best_f = f;
329*c40b6df8SAnup Patel 		}
330*c40b6df8SAnup Patel 	}
331*c40b6df8SAnup Patel 
332*c40b6df8SAnup Patel 	c->divr = best_r - 1;
333*c40b6df8SAnup Patel 	c->divf = best_f - 1;
334*c40b6df8SAnup Patel 
335*c40b6df8SAnup Patel 	post_divr_freq = div_u64(parent_rate, best_r);
336*c40b6df8SAnup Patel 
337*c40b6df8SAnup Patel 	/* Pick the best PLL jitter filter */
338*c40b6df8SAnup Patel 	c->range = __wrpll_calc_filter_range(post_divr_freq);
339*c40b6df8SAnup Patel 
340*c40b6df8SAnup Patel 	return 0;
341*c40b6df8SAnup Patel }
342*c40b6df8SAnup Patel 
343*c40b6df8SAnup Patel /**
344*c40b6df8SAnup Patel  * analogbits_wrpll_calc_output_rate() - calculate the PLL's target output rate
345*c40b6df8SAnup Patel  * @c: ptr to a struct analogbits_wrpll_cfg record to read from
346*c40b6df8SAnup Patel  * @parent_rate: PLL refclk rate
347*c40b6df8SAnup Patel  *
348*c40b6df8SAnup Patel  * Given a pointer to the PLL's current input configuration @c and the
349*c40b6df8SAnup Patel  * PLL's input reference clock rate @parent_rate (before the R
350*c40b6df8SAnup Patel  * pre-divider), calculate the PLL's output clock rate (after the Q
351*c40b6df8SAnup Patel  * post-divider)
352*c40b6df8SAnup Patel  *
353*c40b6df8SAnup Patel  * Context: Any context.  Caller must protect the memory pointed to by @c
354*c40b6df8SAnup Patel  *          from simultaneous modification.
355*c40b6df8SAnup Patel  *
356*c40b6df8SAnup Patel  * Return: the PLL's output clock rate, in Hz.
357*c40b6df8SAnup Patel  */
analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg * c,unsigned long parent_rate)358*c40b6df8SAnup Patel unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
359*c40b6df8SAnup Patel 						unsigned long parent_rate)
360*c40b6df8SAnup Patel {
361*c40b6df8SAnup Patel 	u8 fbdiv;
362*c40b6df8SAnup Patel 	u64 n;
363*c40b6df8SAnup Patel 
364*c40b6df8SAnup Patel 	WARN(c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK,
365*c40b6df8SAnup Patel 	     "external feedback mode not yet supported");
366*c40b6df8SAnup Patel 
367*c40b6df8SAnup Patel 	fbdiv = __wrpll_calc_fbdiv(c);
368*c40b6df8SAnup Patel 	n = parent_rate * fbdiv * (c->divf + 1);
369*c40b6df8SAnup Patel 	n = div_u64(n, (c->divr + 1));
370*c40b6df8SAnup Patel 	n >>= c->divq;
371*c40b6df8SAnup Patel 
372*c40b6df8SAnup Patel 	return n;
373*c40b6df8SAnup Patel }
374*c40b6df8SAnup Patel 
375*c40b6df8SAnup Patel /**
376*c40b6df8SAnup Patel  * analogbits_wrpll_calc_max_lock_us() - return the time for the PLL to lock
377*c40b6df8SAnup Patel  * @c: ptr to a struct analogbits_wrpll_cfg record to read from
378*c40b6df8SAnup Patel  *
379*c40b6df8SAnup Patel  * Return the minimum amount of time (in microseconds) that the caller
380*c40b6df8SAnup Patel  * must wait after reprogramming the PLL to ensure that it is locked
381*c40b6df8SAnup Patel  * to the input frequency and stable.  This is likely to depend on the DIVR
382*c40b6df8SAnup Patel  * value; this is under discussion with the manufacturer.
383*c40b6df8SAnup Patel  *
384*c40b6df8SAnup Patel  * Return: the minimum amount of time the caller must wait for the PLL
385*c40b6df8SAnup Patel  *         to lock (in microseconds)
386*c40b6df8SAnup Patel  */
analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg * c)387*c40b6df8SAnup Patel unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c)
388*c40b6df8SAnup Patel {
389*c40b6df8SAnup Patel 	return MAX_LOCK_US;
390*c40b6df8SAnup Patel }
391