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Searched refs:dsaf_read_dev (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_gmac.c101 porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG); in hns_gmac_get_en()
149 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); in hns_gmac_config_pad_and_crc()
168 tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG); in hns_gmac_tx_loop_pkt_dis()
201 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); in hns_gmac_port_mode_get()
202 recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG); in hns_gmac_port_mode_get()
228 pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); in hns_gmac_pause_frm_cfg()
240 pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); in hns_gmac_get_pausefrm_cfg()
316 val = dsaf_read_dev(drv, GMAC_FIFO_STATE_REG); in hns_gmac_wait_fifo_clean()
371 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG); in hns_gmac_update_stats()
373 += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG); in hns_gmac_update_stats()
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H A Dhns_dsaf_ppe.c37 reg_value = dsaf_read_dev(ppe_cb, in hns_ppe_set_indir_table()
167 u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); in hns_ppe_set_qid()
279 val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU; in hns_ppe_wait_tx_fifo_clean()
416 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); in hns_ppe_update_stats()
418 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); in hns_ppe_update_stats()
420 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); in hns_ppe_update_stats()
422 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); in hns_ppe_update_stats()
424 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); in hns_ppe_update_stats()
426 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); in hns_ppe_update_stats()
428 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); in hns_ppe_update_stats()
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H A Dhns_dsaf_rcb.c45 fbd_num += dsaf_read_dev(qs[i], in hns_rcb_wait_fbd_clean()
48 fbd_num += dsaf_read_dev(qs[i], in hns_rcb_wait_fbd_clean()
66 tail = dsaf_read_dev(&qs->tx_ring, RCB_REG_TAIL); in hns_rcb_wait_tx_ring_clean()
69 head = dsaf_read_dev(&qs->tx_ring, RCB_REG_HEAD); in hns_rcb_wait_tx_ring_clean()
98 tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG); in hns_rcb_reset_ring_hw()
107 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST); in hns_rcb_reset_ring_hw()
116 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST); in hns_rcb_reset_ring_hw()
376 reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG); in hns_rcb_common_init_hw()
558 return dsaf_read_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4); in hns_rcb_get_rx_coalesced_frames()
574 return dsaf_read_dev(rcb_common, reg); in hns_rcb_get_tx_coalesced_frames()
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H A Dhns_dsaf_main.c334 o_sbm_cfg = dsaf_read_dev(dsaf_dev, in hns_dsaf_sbm_cfg()
401 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsaf_sbm_bp_wl_cfg()
411 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsaf_sbm_bp_wl_cfg()
419 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsaf_sbm_bp_wl_cfg()
427 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsaf_sbm_bp_wl_cfg()
438 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsaf_sbm_bp_wl_cfg()
451 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsaf_sbm_bp_wl_cfg()
462 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsaf_sbm_bp_wl_cfg()
480 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsafv2_sbm_bp_wl_cfg()
490 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); in hns_dsafv2_sbm_bp_wl_cfg()
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H A Dhns_dsaf_xgmac.c185 u32 origin = dsaf_read_dev(drv, XGMAC_PMA_FEC_CONTROL_REG); in hns_xgmac_pma_fec_enable()
234 u32 origin = dsaf_read_dev(drv, XGMAC_MAC_CONTROL_REG); in hns_xgmac_config_pad_and_crc()
251 u32 origin = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG); in hns_xgmac_pausefrm_cfg()
430 ctrl_val = dsaf_read_dev(drv, XGMAC_MAC_CONTROL_REG); in hns_xgmac_get_info()
434 pause_time = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_TIME_REG); in hns_xgmac_get_info()
437 port_mode = dsaf_read_dev(drv, XGMAC_PORT_MODE_REG); in hns_xgmac_get_info()
445 pause_ctrl = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG); in hns_xgmac_get_info()
461 pause_ctrl = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG); in hns_xgmac_get_pausefrm_cfg()
475 *link_stat = dsaf_read_dev(drv, XGMAC_LINK_STATUS_REG); in hns_xgmac_get_link_status()
491 regs[0] = dsaf_read_dev(drv, XGMAC_INT_STATUS_REG); in hns_xgmac_get_regs()
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H A Dhns_dsaf_main.h407 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); in hns_dsaf_tbl_tcam_load_pul()
H A Dhns_dsaf_reg.h1040 #define dsaf_read_dev(a, reg) \ macro