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Searched refs:dramtmg (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c56 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
58 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
61 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
63 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
65 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
68 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
71 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), in mctl_set_timing_params()
H A Dddr3_1333.c59 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
61 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
64 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
66 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
68 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
71 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
74 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), in mctl_set_timing_params()
H A Dlpddr3_stock.c55 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
57 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
60 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
62 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
64 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
67 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
70 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), in mctl_set_timing_params()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun50i_h6.c245 &mctl_ctl->dramtmg[0]); in mctl_set_timing_lpddr3()
246 writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); in mctl_set_timing_lpddr3()
248 &mctl_ctl->dramtmg[2]); in mctl_set_timing_lpddr3()
249 writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); in mctl_set_timing_lpddr3()
251 &mctl_ctl->dramtmg[4]); in mctl_set_timing_lpddr3()
253 &mctl_ctl->dramtmg[5]); in mctl_set_timing_lpddr3()
255 writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); in mctl_set_timing_lpddr3()
257 &mctl_ctl->dramtmg[8]); in mctl_set_timing_lpddr3()
258 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_lpddr3()
H A Ddram_sun9i.c535 &mctl_ctl->dramtmg[0]); in mctl_channel_init()
538 &mctl_ctl->dramtmg[1]); in mctl_channel_init()
541 &mctl_ctl->dramtmg[2]); in mctl_channel_init()
547 &mctl_ctl->dramtmg[3]); in mctl_channel_init()
550 &mctl_ctl->dramtmg[4]); in mctl_channel_init()
553 &mctl_ctl->dramtmg[5]); in mctl_channel_init()
567 writel((MCTL_DIV32(tXSDLL) << 0), &mctl_ctl->dramtmg[8]); in mctl_channel_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sunxi_dw.h93 u32 dramtmg[9]; /* 0x58 DRAM timing registers */ member
H A Ddram_sun50i_h6.h91 u32 dramtmg[17]; /* 0x100 */ member
H A Ddram_sun9i.h63 u32 dramtmg[9]; /* 0x100 DRAM timing register */ member