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Searched refs:div4 (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclock.h32 unsigned int div4; member
68 unsigned int div4; member
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dda8xx-cfgchip.txt43 - clock-names: shall be "pll0_sysclk3", "div4.5"
71 div4p5_clk: div4.5 {
81 clock-names = "pll0_sysclk3", "div4.5";
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier.h122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
124 UNIPHIER_CLK_DIV(parent, div4)
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock_defs.h38 u32 div4; /* 60 */ member
/openbmc/u-boot/arch/arm/dts/
H A Dls1021a.dtsi124 "cga-pll1-div4";
139 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
H A Dda850.dtsi354 div4p5_clk: div4.5 {
364 clock-names = "pll0_sysclk3", "div4.5";
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c132 offset = pllctl_reg(data->pll, div4) + (i - 3); in configure_main_pll()
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-clocks.dtsi315 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
324 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
H A Dam43xx-clocks.dtsi370 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
379 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
/openbmc/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi400 div4p5_clk: div4.5 {
410 clock-names = "pll0_sysclk3", "div4.5";
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-oneplus-common.dtsi43 divclk4: div4-clk {
/openbmc/linux/drivers/video/fbdev/
H A Damifb.c551 #define div4(v) ((v)>>2) macro