| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | gen8_engine_cs.c | 16 u32 *cs, flags = 0; in gen8_emit_flush_rcs() local
58 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
59 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
60 return PTR_ERR(cs); in gen8_emit_flush_rcs()
63 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
66 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, in gen8_emit_flush_rcs()
69 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); in gen8_emit_flush_rcs()
72 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); in gen8_emit_flush_rcs()
74 intel_ring_advance(rq, cs); in gen8_emit_flush_rcs()
81 u32 cmd, *cs; in gen8_emit_flush_xcs() local
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| H A D | gen6_engine_cs.c | 60 u32 *cs; in gen6_emit_post_sync_nonzero_flush() local
62 cs = intel_ring_begin(rq, 6); in gen6_emit_post_sync_nonzero_flush()
63 if (IS_ERR(cs)) in gen6_emit_post_sync_nonzero_flush()
64 return PTR_ERR(cs); in gen6_emit_post_sync_nonzero_flush()
66 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
67 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; in gen6_emit_post_sync_nonzero_flush()
68 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; in gen6_emit_post_sync_nonzero_flush()
69 *cs++ = 0; /* low dword */ in gen6_emit_post_sync_nonzero_flush()
70 *cs++ = 0; /* high dword */ in gen6_emit_post_sync_nonzero_flush()
71 *cs++ = MI_NOOP; in gen6_emit_post_sync_nonzero_flush()
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| H A D | gen2_engine_cs.c | 19 u32 cmd, *cs; in gen2_emit_flush() local
25 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
26 if (IS_ERR(cs)) in gen2_emit_flush()
27 return PTR_ERR(cs); in gen2_emit_flush()
29 *cs++ = cmd; in gen2_emit_flush()
31 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
32 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
33 *cs++ = 0; in gen2_emit_flush()
34 *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen2_emit_flush()
36 *cs++ = cmd; in gen2_emit_flush()
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| H A D | gen7_renderclear.c | 102 static u32 batch_offset(const struct batch_chunk *bc, u32 *cs) in batch_offset() argument
104 return (cs - bc->start) * sizeof(*bc->start) + bc->offset; in batch_offset()
148 u32 *cs = batch_alloc_items(state, 32, 8); in gen7_fill_surface_state() local
149 u32 offset = batch_offset(state, cs); in gen7_fill_surface_state()
155 *cs++ = SURFACE_2D << 29 | in gen7_fill_surface_state()
159 *cs++ = batch_addr(state) + dst_offset; in gen7_fill_surface_state()
161 *cs++ = ((surface_h / 4 - 1) << 16) | (surface_w / 4 - 1); in gen7_fill_surface_state()
162 *cs++ = surface_w; in gen7_fill_surface_state()
163 *cs++ = 0; in gen7_fill_surface_state()
164 *cs++ = 0; in gen7_fill_surface_state()
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| H A D | intel_migrate.c | 336 u32 *cs; in emit_no_arbitration() local
338 cs = intel_ring_begin(rq, 2); in emit_no_arbitration()
339 if (IS_ERR(cs)) in emit_no_arbitration()
340 return PTR_ERR(cs); in emit_no_arbitration()
343 *cs++ = MI_ARB_ON_OFF; in emit_no_arbitration()
344 *cs++ = MI_NOOP; in emit_no_arbitration()
345 intel_ring_advance(rq, cs); in emit_no_arbitration()
376 u32 *hdr, *cs; in emit_pte() local
403 cs = intel_ring_begin(rq, I915_EMIT_PTE_NUM_DWORDS); in emit_pte()
404 if (IS_ERR(cs)) in emit_pte()
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_redist.c | 17 static uint32_t mask_group(GICv3CPUState *cs, MemTxAttrs attrs) in mask_group() argument
24 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in mask_group()
26 return cs->gicr_igroupr0; in mask_group()
31 static int gicr_ns_access(GICv3CPUState *cs, int irq) in gicr_ns_access() argument
35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
38 static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, in gicr_write_bitmap_reg() argument
42 val &= mask_group(cs, attrs); in gicr_write_bitmap_reg()
44 gicv3_redist_update(cs); in gicr_write_bitmap_reg()
47 static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, in gicr_write_set_bitmap_reg() argument
51 val &= mask_group(cs, attrs); in gicr_write_set_bitmap_reg()
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| H A D | arm_gicv3_cpuif.c | 50 static inline int icv_min_vbpr(GICv3CPUState *cs) in icv_min_vbpr() argument
52 return 7 - cs->vprebits; in icv_min_vbpr()
55 static inline int ich_num_aprs(GICv3CPUState *cs) in ich_num_aprs() argument
58 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
59 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
107 static int read_vbpr(GICv3CPUState *cs, int grp) in read_vbpr() argument
113 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
116 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, in read_vbpr()
121 static void write_vbpr(GICv3CPUState *cs, int grp, int value) in write_vbpr() argument
126 int min = icv_min_vbpr(cs); in write_vbpr()
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| H A D | arm_gicv3.c | 24 static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi) in irqbetter() argument
33 if (prio != cs->hppi.prio) { in irqbetter()
34 return prio < cs->hppi.prio; in irqbetter()
41 if (nmi != cs->hppi.nmi) { in irqbetter()
49 if (irq <= cs->hppi.irq) { in irqbetter()
101 static uint32_t gicr_int_pending(GICv3CPUState *cs) in gicr_int_pending() argument
116 pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level); in gicr_int_pending()
117 pend &= cs->gicr_ienabler0; in gicr_int_pending()
118 pend &= ~cs->gicr_iactiver0; in gicr_int_pending()
120 if (cs->gic->gicd_ctlr & GICD_CTLR_DS) { in gicr_int_pending()
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| /openbmc/linux/kernel/time/ |
| H A D | clocksource.c | 23 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
25 u64 delta = clocksource_delta(end, start, cs->mask); in cycles_to_nsec_safe()
27 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
28 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
30 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
161 static void __clocksource_change_rating(struct clocksource *cs, int rating);
181 static void __clocksource_unstable(struct clocksource *cs) in __clocksource_unstable() argument
183 cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG); in __clocksource_unstable()
184 cs->flags |= CLOCK_SOURCE_UNSTABLE; in __clocksource_unstable()
190 if (list_empty(&cs->list)) { in __clocksource_unstable()
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| /openbmc/qemu/target/i386/hvf/ |
| H A D | x86hvf.c | 35 void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg, in hvf_set_segment() argument
42 if (!qseg->selector && !x86_is_real(cs) && !is_tr) { in hvf_set_segment()
73 void hvf_put_xsave(CPUState *cs) in hvf_put_xsave() argument
75 void *xsave = X86_CPU(cs)->env.xsave_buf; in hvf_put_xsave()
76 uint32_t xsave_len = X86_CPU(cs)->env.xsave_buf_len; in hvf_put_xsave()
78 x86_cpu_xsave_all_areas(X86_CPU(cs), xsave, xsave_len); in hvf_put_xsave()
80 if (hv_vcpu_write_fpstate(cs->accel->fd, xsave, xsave_len)) { in hvf_put_xsave()
85 static void hvf_put_segments(CPUState *cs) in hvf_put_segments() argument
87 CPUX86State *env = &X86_CPU(cs)->env; in hvf_put_segments()
90 wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); in hvf_put_segments()
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| /openbmc/qemu/target/i386/tcg/sysemu/ |
| H A D | smm_helper.c | 38 CPUState *cs = CPU(cpu); in do_smm_enter() local
60 x86_stw_phys(cs, sm_state + offset, dt->selector); in do_smm_enter()
61 x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff); in do_smm_enter()
62 x86_stl_phys(cs, sm_state + offset + 4, dt->limit); in do_smm_enter()
63 x86_stq_phys(cs, sm_state + offset + 8, dt->base); in do_smm_enter()
66 x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base); in do_smm_enter()
67 x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit); in do_smm_enter()
69 x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector); in do_smm_enter()
70 x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base); in do_smm_enter()
71 x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit); in do_smm_enter()
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| /openbmc/qemu/target/loongarch/kvm/ |
| H A D | kvm.c | 37 static int kvm_get_stealtime(CPUState *cs) in kvm_get_stealtime() argument
39 CPULoongArchState *env = cpu_env(cs); in kvm_get_stealtime()
47 err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); in kvm_get_stealtime()
52 err = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, attr); in kvm_get_stealtime()
61 static int kvm_set_stealtime(CPUState *cs) in kvm_set_stealtime() argument
63 CPULoongArchState *env = cpu_env(cs); in kvm_set_stealtime()
71 err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); in kvm_set_stealtime()
76 err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); in kvm_set_stealtime()
86 static int kvm_loongarch_get_regs_core(CPUState *cs) in kvm_loongarch_get_regs_core() argument
91 CPULoongArchState *env = cpu_env(cs); in kvm_loongarch_get_regs_core()
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| /openbmc/linux/kernel/cgroup/ |
| H A D | cpuset.c | 229 static inline struct cpuset *parent_cs(struct cpuset *cs) in parent_cs() argument
231 return css_cs(cs->css.parent); in parent_cs()
236 struct cpuset *cs = task_cs(p); in inc_dl_tasks_cs() local
238 cs->nr_deadline_tasks++; in inc_dl_tasks_cs()
243 struct cpuset *cs = task_cs(p); in dec_dl_tasks_cs() local
245 cs->nr_deadline_tasks--; in dec_dl_tasks_cs()
261 static inline bool is_cpuset_online(struct cpuset *cs) in is_cpuset_online() argument
263 return test_bit(CS_ONLINE, &cs->flags) && !css_is_dying(&cs->css); in is_cpuset_online()
266 static inline int is_cpu_exclusive(const struct cpuset *cs) in is_cpu_exclusive() argument
268 return test_bit(CS_CPU_EXCLUSIVE, &cs->flags); in is_cpu_exclusive()
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| /openbmc/qemu/semihosting/ |
| H A D | syscalls.c | 25 static int validate_strlen(CPUState *cs, target_ulong str, target_ulong tlen) in validate_strlen() argument
27 CPUArchState *env G_GNUC_UNUSED = cpu_env(cs); in validate_strlen()
53 static int validate_lock_user_string(char **pstr, CPUState *cs, in validate_lock_user_string() argument
56 int ret = validate_strlen(cs, tstr, tlen); in validate_lock_user_string()
57 CPUArchState *env G_GNUC_UNUSED = cpu_env(cs); in validate_lock_user_string()
74 static int copy_stat_to_user(CPUState *cs, target_ulong addr, in copy_stat_to_user() argument
77 CPUArchState *env G_GNUC_UNUSED = cpu_env(cs); in copy_stat_to_user()
120 static void gdb_open_cb(CPUState *cs, uint64_t ret, int err) in gdb_open_cb() argument
127 gdb_open_complete(cs, ret, err); in gdb_open_cb()
130 static void gdb_open(CPUState *cs, gdb_syscall_complete_cb complete, in gdb_open() argument
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| H A D | arm-compat-semi.c | 143 static LayoutInfo common_semi_find_bases(CPUState *cs) in common_semi_find_bases() argument
150 fv = address_space_to_flatview(cs->as); in common_semi_find_bases()
214 static inline uint32_t get_swi_errno(CPUState *cs) in get_swi_errno() argument
217 TaskState *ts = get_task_state(cs); in get_swi_errno()
225 static void common_semi_cb(CPUState *cs, uint64_t ret, int err) in common_semi_cb() argument
229 TaskState *ts = get_task_state(cs); in common_semi_cb()
235 common_semi_set_ret(cs, ret); in common_semi_cb()
242 static void common_semi_dead_cb(CPUState *cs, uint64_t ret, int err) in common_semi_dead_cb() argument
244 common_semi_set_ret(cs, 0xdeadbeef); in common_semi_dead_cb()
251 static void common_semi_rw_cb(CPUState *cs, uint64_t ret, int err) in common_semi_rw_cb() argument
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| /openbmc/linux/drivers/gpu/drm/i915/pxp/ |
| H A D | intel_pxp_cmd.c | 23 static u32 *pxp_emit_session_selection(u32 *cs, u32 idx) in pxp_emit_session_selection() argument
25 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
28 *cs++ = MI_FLUSH_DW; in pxp_emit_session_selection()
29 *cs++ = 0; in pxp_emit_session_selection()
30 *cs++ = 0; in pxp_emit_session_selection()
33 *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx); in pxp_emit_session_selection()
35 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
38 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN | in pxp_emit_session_selection()
40 *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT; in pxp_emit_session_selection()
41 *cs++ = 0; in pxp_emit_session_selection()
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| /openbmc/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
82 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
84 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
85 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
86 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
110 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
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| /openbmc/linux/drivers/scsi/ |
| H A D | myrs.c | 104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
108 union myrs_cmd_mbox *next_mbox = cs->next_cmd_mbox; in myrs_qcmd()
110 cs->write_cmd_mbox(next_mbox, mbox); in myrs_qcmd()
112 if (cs->prev_cmd_mbox1->words[0] == 0 || in myrs_qcmd()
113 cs->prev_cmd_mbox2->words[0] == 0) in myrs_qcmd()
114 cs->get_cmd_mbox(base); in myrs_qcmd()
116 cs->prev_cmd_mbox2 = cs->prev_cmd_mbox1; in myrs_qcmd()
117 cs->prev_cmd_mbox1 = next_mbox; in myrs_qcmd()
119 if (++next_mbox > cs->last_cmd_mbox) in myrs_qcmd()
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| /openbmc/qemu/target/mips/ |
| H A D | kvm.c | 42 unsigned long kvm_arch_vcpu_id(CPUState *cs) in kvm_arch_vcpu_id() argument
44 return cs->cpu_index; in kvm_arch_vcpu_id()
64 int kvm_arch_init_vcpu(CPUState *cs) in kvm_arch_init_vcpu() argument
66 CPUMIPSState *env = cpu_env(cs); in kvm_arch_init_vcpu()
69 qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); in kvm_arch_init_vcpu()
72 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); in kvm_arch_init_vcpu()
81 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); in kvm_arch_init_vcpu()
93 int kvm_arch_destroy_vcpu(CPUState *cs) in kvm_arch_destroy_vcpu() argument
114 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) in kvm_arch_insert_sw_breakpoint() argument
120 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) in kvm_arch_remove_sw_breakpoint() argument
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| /openbmc/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_write_leveling.c | 46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
106 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
115 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
127 cs, pup); in ddr3_write_leveling_hw()
128 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
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| H A D | ddr3_read_leveling.c | 44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
97 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
106 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
121 cs, pup); in ddr3_read_leveling_hw()
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| /openbmc/qemu/linux-user/ppc/ |
| H A D | cpu_loop.c | 70 CPUState *cs = env_cpu(env); in cpu_loop() local
77 cpu_exec_start(cs); in cpu_loop()
78 trapnr = cpu_exec(cs); in cpu_loop()
79 cpu_exec_end(cs); in cpu_loop()
80 process_queued_cpu_work(cs); in cpu_loop()
88 cpu_abort(cs, "Critical interrupt while in user mode. " in cpu_loop()
92 cpu_abort(cs, "Machine check exception while in user mode. " in cpu_loop()
102 cpu_abort(cs, "External interrupt while in user mode. " in cpu_loop()
188 cpu_abort(cs, "Unknown program exception (%02x)\n", in cpu_loop()
202 cpu_abort(cs, "Syscall exception while in user mode. " in cpu_loop()
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| /openbmc/linux/sound/core/ |
| H A D | pcm_iec958.c | 29 int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len) in snd_pcm_create_iec958_consumer_default() argument
34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
36 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
38 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; in snd_pcm_create_iec958_consumer_default()
39 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; in snd_pcm_create_iec958_consumer_default()
42 cs[4] = IEC958_AES4_CON_WORDLEN_NOTID; in snd_pcm_create_iec958_consumer_default()
49 u8 *cs, size_t len) in fill_iec958_consumer() argument
54 if ((cs[3] & IEC958_AES3_CON_FS) == IEC958_AES3_CON_FS_NOTID) { in fill_iec958_consumer()
83 cs[3] &= ~IEC958_AES3_CON_FS; in fill_iec958_consumer()
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| /openbmc/qemu/target/i386/kvm/ |
| H A D | xen-emu.c | 47 static int vcpuop_stop_singleshot_timer(CPUState *cs);
55 static bool kvm_gva_to_gpa(CPUState *cs, uint64_t gva, uint64_t *gpa, in kvm_gva_to_gpa() argument
66 if (kvm_vcpu_ioctl(cs, KVM_TRANSLATE, &tr) || !tr.valid || in kvm_gva_to_gpa()
74 static int kvm_gva_rw(CPUState *cs, uint64_t gva, void *_buf, size_t sz, in kvm_gva_rw() argument
82 if (!kvm_gva_to_gpa(cs, gva, &gpa, &len, is_write)) { in kvm_gva_rw()
99 static inline int kvm_copy_from_gva(CPUState *cs, uint64_t gva, void *buf, in kvm_copy_from_gva() argument
102 return kvm_gva_rw(cs, gva, buf, sz, false); in kvm_copy_from_gva()
105 static inline int kvm_copy_to_gva(CPUState *cs, uint64_t gva, void *buf, in kvm_copy_to_gva() argument
108 return kvm_gva_rw(cs, gva, buf, sz, true); in kvm_copy_to_gva()
188 int kvm_xen_init_vcpu(CPUState *cs) in kvm_xen_init_vcpu() argument
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| /openbmc/u-boot/arch/arm/mach-omap2/omap3/ |
| H A D | sdrc.c | 40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
68 u32 get_sdr_cs_size(u32 cs) in get_sdr_cs_size() argument
73 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; in get_sdr_cs_size()
83 u32 get_sdr_cs_offset(u32 cs) in get_sdr_cs_offset() argument
87 if (!cs) in get_sdr_cs_offset()
101 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, in write_sdrc_timings() argument
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
108 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
109 writel(CMD_NOP, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
110 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
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