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Searched refs:config_2 (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
115 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
147 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
179 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
211 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
243 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
275 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
307 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
/openbmc/u-boot/board/freescale/p1_twr/
H A Dddr.c24 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, in fixed_sdram()
28 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, in fixed_sdram()
/openbmc/u-boot/drivers/ddr/fsl/
H A Darm_ddr_gen3.c72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
77 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
82 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
87 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
H A Dmpc85xx_ddr_gen3.c95 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
100 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
105 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
110 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
H A Dfsl_ddr_gen4.c121 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
131 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
141 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
151 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
H A Dinteractive.c612 CFG_REGS_CS(0, config_2), in print_fsl_memctl_config_regs()
616 CFG_REGS_CS(1, config_2), in print_fsl_memctl_config_regs()
621 CFG_REGS_CS(2, config_2), in print_fsl_memctl_config_regs()
626 CFG_REGS_CS(3, config_2), in print_fsl_memctl_config_regs()
703 CFG_REGS_CS(0, config_2), in fsl_ddr_regs_edit()
707 CFG_REGS_CS(1, config_2), in fsl_ddr_regs_edit()
712 CFG_REGS_CS(2, config_2), in fsl_ddr_regs_edit()
717 CFG_REGS_CS(3, config_2), in fsl_ddr_regs_edit()
H A Dctrl_regs.c253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dddr.h54 .cs[0].config_2 = 0,
56 .cs[1].config_2 = 0,
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dddr.c84 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, in fixed_sdram()
88 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, in fixed_sdram()
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dddr.c20 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
47 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c23 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
50 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dddr.c216 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, in fixed_sdram()
220 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, in fixed_sdram()
/openbmc/linux/drivers/scsi/
H A Dqla1280.c1943 nv->bus[0].config_2.async_data_setup_time); in qla1280_print_settings()
1945 nv->bus[1].config_2.async_data_setup_time); in qla1280_print_settings()
1948 nv->bus[0].config_2.req_ack_active_negation); in qla1280_print_settings()
1950 nv->bus[1].config_2.req_ack_active_negation); in qla1280_print_settings()
1953 nv->bus[0].config_2.data_line_active_negation); in qla1280_print_settings()
1955 nv->bus[1].config_2.data_line_active_negation); in qla1280_print_settings()
2040 nv->bus[bus].config_2.req_ack_active_negation = 1; in qla1280_set_defaults()
2041 nv->bus[bus].config_2.data_line_active_negation = 1; in qla1280_set_defaults()
2047 nv->bus[bus].config_2.async_data_setup_time = 6; in qla1280_set_defaults()
2051 nv->bus[bus].config_2.async_data_setup_time = 8; in qla1280_set_defaults()
[all …]
H A Dqla1280.h435 } config_2; /* 28 */ member
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dddr.c21 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
/openbmc/u-boot/include/
H A Dfsl_ddr_sdram.h246 unsigned int config_2; member
/openbmc/linux/
H A Dopengrok0.0.log[all...]