SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

show more ...

Merge git://git.denx.de/u-boot-fsl-qoriq

drivers/ddr/fsl: Add 3DS RDIMM support

On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.

Signed-off-by: York Sun <york.sun

drivers/ddr/fsl: Add 3DS RDIMM support

On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.

Signed-off-by: York Sun <york.sun@nxp.com>

show more ...

drivers/ddr/fsl: Fix DDR4 RDIMM support

For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional regi

drivers/ddr/fsl: Fix DDR4 RDIMM support

For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.

Signed-off-by: York Sun <york.sun@nxp.com>

show more ...

arm: freescale: Rename initdram() to fsl_initdram()

This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.

Sign

arm: freescale: Rename initdram() to fsl_initdram()

This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.

Signed-off-by: Simon Glass <sjg@chromium.org>

show more ...

Merge git://git.denx.de/u-boot-fsl-qoriq

armv8/fsl_lsch2: Add chip power supply voltage setup

Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed a

armv8/fsl_lsch2: Add chip power supply voltage setup

Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.

Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-fsl-qoriq

fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum

- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move

fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum

- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>

driver/ddr/fsl: Add more debug registers

32 more debug registers are added for newer DDR controllers.

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

driver/ddr/fsl: Add workaround for erratum A-009801

The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.

Signed-off-by:

driver/ddr/fsl: Add workaround for erratum A-009801

The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

drivers/ddr/fsl: update workaround for erratum A-008511

Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.

Signed-off-by:

drivers/ddr/fsl: update workaround for erratum A-008511

Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

armv8/ls1043: Add workaround for DDR erratum A-008850

Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround

armv8/ls1043: Add workaround for DDR erratum A-008850

Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete

Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7

driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete

Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

driver/ddr/fsl: Add workaround for A009663

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired va

driver/ddr/fsl: Add workaround for A009663

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

Add more SPDX-License-Identifier tags

In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert

Add more SPDX-License-Identifier tags

In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

driver/ddr/fsl: Update DDR4 RTT values

DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun <yorksun@freescale.com>

Merge git://git.denx.de/u-boot