| /openbmc/linux/drivers/clk/ti/ |
| H A D | clk-33xx.c | 272 struct clk *clk1, *clk2; in am33xx_dt_clk_init() local
293 clk2 = clk_get_sys(NULL, "timer3_fck"); in am33xx_dt_clk_init()
294 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
296 clk2 = clk_get_sys(NULL, "timer6_fck"); in am33xx_dt_clk_init()
297 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
306 clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); in am33xx_dt_clk_init()
307 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
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| H A D | clk-43xx.c | 275 struct clk *clk1, *clk2; in am43xx_dt_clk_init() local
297 clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); in am43xx_dt_clk_init()
298 clk_set_parent(clk1, clk2); in am43xx_dt_clk_init()
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-sp804.c | 259 struct clk *clk1, *clk2; in sp804_of_init() local
284 clk2 = of_clk_get(np, 1); in sp804_of_init()
285 if (IS_ERR(clk2)) { in sp804_of_init()
287 (int)PTR_ERR(clk2)); in sp804_of_init()
288 clk2 = NULL; in sp804_of_init()
291 clk2 = clk1; in sp804_of_init()
302 ret = sp804_clockevents_init(timer2_base, irq, clk2, name); in sp804_of_init()
317 name, clk2, 1); in sp804_of_init()
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| /openbmc/u-boot/drivers/spi/ |
| H A D | mscc_bb_spi.c | 25 u32 clk2; /* Clock value 2nd phase */ member
42 priv->clk2 = 0; in mscc_bb_spi_cs_activate()
46 priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK; in mscc_bb_spi_cs_activate()
66 writel(priv->svalue | priv->clk2, priv->regs); in mscc_bb_spi_cs_activate()
159 writel(value | priv->clk2, priv->regs); in mscc_bb_spi_xfer()
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| /openbmc/linux/drivers/phy/allwinner/ |
| H A D | phy-sun4i-usb.c | 125 struct clk *clk2; member
268 ret = clk_prepare_enable(phy->clk2); in sun4i_usb_phy_init()
276 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
288 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
297 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
306 ret = clk_prepare_enable(phy2->clk2); in sun4i_usb_phy_init()
311 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
322 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_init()
397 clk_disable_unprepare(phy->clk2); in sun4i_usb_phy_exit()
818 phy->clk2 = devm_clk_get(dev, name); in sun4i_usb_phy_probe()
[all …]
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 815 struct clk *clk1, *clk2; in rk3188a_clk_init() local
835 clk2 = __clk_lookup("gpll"); in rk3188a_clk_init()
836 if (clk1 && clk2) { in rk3188a_clk_init()
839 ret = clk_set_parent(clk1, clk2); in rk3188a_clk_init()
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| /openbmc/qemu/docs/devel/ |
| H A D | clocks.rst | 218 Given two clocks ``clk1``, and ``clk2``, ``clock_set_source(clk2, clk1);``
219 configures ``clk2`` to follow the ``clk1`` period changes. Every time ``clk1``
220 is updated, ``clk2`` will be updated too.
224 device clock. For example, to connect the input clock ``clk2`` of
229 qdev_connect_clock_in(devB, "clk2", qdev_get_clock_out(devA, "clk1"))
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| /openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
| H A D | lpc4350-hitex-eval.dts | 230 pins = "clk0", "clk1", "clk2", "clk3";
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| H A D | lpc4357-ea4357-devkit.dts | 260 pins = "clk0", "clk1", "clk2", "clk3";
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| /openbmc/linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra30-colibri.dtsi | 259 clk2-out-pw5 {
620 clk2-req-pcc5 {
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| H A D | tegra30-apalis-v1.1.dtsi | 152 clk2-out-pw5 {
446 clk2-req-pcc5 {
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| H A D | tegra30-apalis.dtsi | 151 clk2-out-pw5 {
445 clk2-req-pcc5 {
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| H A D | tegra124-apalis-v1.2.dtsi | 348 clk2-out-pw5 { /* D5 GPIO */
397 clk2-req-pcc5 { /* D4 GPIO */
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| H A D | tegra124-apalis.dtsi | 345 clk2-out-pw5 { /* D5 GPIO */
394 clk2-req-pcc5 { /* D4 GPIO */
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dra7xx-clocks.dtsi | 823 hdmi_clk2_div: clock-hdmi-clk2-div {
861 video1_clk2_div: clock-video1-clk2-div {
879 video2_clk2_div: clock-video2-clk2-div {
1001 sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | clk-rpmh.c | 371 DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-lpc18xx.c | 418 LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
627 LPC18XX_PIN(clk2, PIN_CLK2),
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| /openbmc/linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra210.dtsi | 849 pins = "pex-bias", "pex-clk1", "pex-clk2";
854 pins = "pex-bias", "pex-clk1", "pex-clk2";
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| /openbmc/linux/arch/arm64/boot/dts/qcom/ |
| H A D | msm8939.dtsi | 1594 "mi2s-bit-clk2",
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| H A D | msm8916.dtsi | 2015 "mi2s-bit-clk2",
|