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Searched refs:bnds (Results 1 – 20 of 20) sorted by relevance

/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
110 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
111 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
112 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
113 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
142 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
143 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c74 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
75 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
78 csn_bnds_backup = regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
79 csn_bnds_t = (unsigned int *) &regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
81 *csn_bnds_t = regs->cs[i].bnds + 0x01000000; in fsl_ddr_set_memctl_regs()
83 *csn_bnds_t = regs->cs[i].bnds + 0x01000100; in fsl_ddr_set_memctl_regs()
86 csn, csn_bnds_backup, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
98 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
103 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen1.c28 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
32 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
36 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
40 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dmpc86xx_ddr.c34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dmpc85xx_ddr_gen2.c49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
61 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dfsl_ddr_gen4.c113 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
118 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
126 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
136 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
138 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
146 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
148 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
477 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds); in fsl_ddr_set_memctl_regs()
479 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Darm_ddr_gen3.c70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
80 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
85 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
H A Dinteractive.c610 CFG_REGS_CS(0, bnds), in print_fsl_memctl_config_regs()
614 CFG_REGS_CS(1, bnds), in print_fsl_memctl_config_regs()
619 CFG_REGS_CS(2, bnds), in print_fsl_memctl_config_regs()
624 CFG_REGS_CS(3, bnds), in print_fsl_memctl_config_regs()
701 CFG_REGS_CS(0, bnds), in fsl_ddr_regs_edit()
705 CFG_REGS_CS(1, bnds), in fsl_ddr_regs_edit()
710 CFG_REGS_CS(2, bnds), in fsl_ddr_regs_edit()
715 CFG_REGS_CS(3, bnds), in fsl_ddr_regs_edit()
H A Dmain.c603 if (reg->cs[j].bnds == 0xffffffff) in fsl_ddr_compute()
605 end = reg->cs[j].bnds & 0xffff; in fsl_ddr_compute()
H A Dctrl_regs.c2528 ddr->cs[i].bnds = (0 in compute_fsl_memctl_config_regs()
2534 ddr->cs[i].bnds = 0xffffffff; in compute_fsl_memctl_config_regs()
2537 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); in compute_fsl_memctl_config_regs()
/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dddr.h49 .cs[0].bnds = 0x0000007F,
50 .cs[1].bnds = 0,
51 .cs[2].bnds = 0,
52 .cs[3].bnds = 0,
/openbmc/u-boot/board/freescale/p1_twr/
H A Dddr.c22 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, in fixed_sdram()
26 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, in fixed_sdram()
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c21 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
48 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
137 ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; in fixed_sdram()
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dddr.c82 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, in fixed_sdram()
86 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, in fixed_sdram()
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dddr.c18 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
45 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dddr.c214 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, in fixed_sdram()
218 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, in fixed_sdram()
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dddr.c19 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
/openbmc/u-boot/include/
H A Dfsl_ddr_sdram.h244 unsigned int bnds; member
/openbmc/rest-dbus/resources/
H A Djsrender.min.js3 …bnds[n-1],d=t.linkCtx;return void 0!==i?n=i={props:{},args:[i]}:s&&(n=s(t.data,t,Z)),o=n.args[0],(… property in C.AnonymousClassba77119e1101
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/js/
H A Djsrender.min.js3 …bnds[n-1],d=t.linkCtx;return void 0!==r?n=r={props:{},args:[r]}:a&&(n=a(t.data,t,ae)),s=n.args[0],… property in V.AnonymousClassdc4085021601