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Searched refs:base_reg (Results 1 – 25 of 69) sorted by relevance

123

/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c232 u64 base_reg; in goya_config_stm() local
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in goya_config_stm()
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dwinmacro.h38 #define LOAD_PT_INS(base_reg) \ argument
39 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
40 ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
41 ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
42 ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
44 #define LOAD_PT_GLOBALS(base_reg) \ argument
45 ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
46 ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
47 ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
48 ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
[all …]
/openbmc/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c394 u64 base_reg; in gaudi_config_stm() local
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in gaudi_config_stm()
405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
413 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
415 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
417 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
419 WREG32(base_reg + 0xE70, 0x10); in gaudi_config_stm()
[all …]
/openbmc/linux/drivers/base/regmap/
H A Dregcache-rbtree.c27 unsigned int base_reg; member
44 *base = rbnode->base_reg; in regcache_rbtree_get_base_top_reg()
45 *top = rbnode->base_reg + ((rbnode->blklen - 1) * map->reg_stride); in regcache_rbtree_get_base_top_reg()
68 unsigned int base_reg, top_reg; in regcache_rbtree_lookup() local
72 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg, in regcache_rbtree_lookup()
74 if (reg >= base_reg && reg <= top_reg) in regcache_rbtree_lookup()
81 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg, in regcache_rbtree_lookup()
83 if (reg >= base_reg && reg <= top_reg) { in regcache_rbtree_lookup()
88 } else if (reg < base_reg) { in regcache_rbtree_lookup()
102 unsigned int base_reg; in regcache_rbtree_insert() local
[all …]
/openbmc/linux/drivers/crypto/intel/keembay/
H A Docs-aes.c206 iowrite32(0x7FF, aes_dev->base_reg + AES_BYTE_ORDER_CFG_OFFSET); in aes_a_set_endianness()
212 iowrite32(AES_ACTIVE_TRIGGER, aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_op_trigger()
219 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_op_termination()
234 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_set_last_gcx()
243 aes_active_reg = ioread32(aes_dev->base_reg + in aes_a_wait_last_gcx()
254 reg = ioread32(aes_dev->base_reg + AES_A_DMA_STATUS_OFFSET); in aes_a_dma_wait_input_buffer_occupancy()
268 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_set_last_gcx_and_adata()
274 iowrite32(0, aes_dev->base_reg + AES_A_DMA_SRC_SIZE_OFFSET); in aes_a_dma_set_xfer_size_zero()
275 iowrite32(0, aes_dev->base_reg + AES_A_DMA_DST_SIZE_OFFSET); in aes_a_dma_set_xfer_size_zero()
282 aes_dev->base_reg + AES_A_DMA_DMA_MODE_OFFSET); in aes_a_dma_active()
[all …]
H A Dkeembay-ocs-ecc.c87 void __iomem *base_reg; member
137 return readl_poll_timeout((dev->base_reg + HW_OFFS_OCS_ECC_STATUS), in ocs_ecc_wait_idle()
146 ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND); in ocs_ecc_cmd_start()
156 iowrite32(op_size | inst, dev->base_reg + HW_OFFS_OCS_ECC_COMMAND); in ocs_ecc_write_cmd_and_data()
159 memcpy_toio(dev->base_reg + HW_OFFS_OCS_ECC_DATA_IN, data_in, in ocs_ecc_write_cmd_and_data()
169 iowrite32(ECC_ENABLE_INTR, ecc_dev->base_reg + HW_OFFS_OCS_ECC_IER); in ocs_ecc_trigger_op()
170 iowrite32(op_size | inst, ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND); in ocs_ecc_trigger_op()
185 memcpy_fromio(cx_out, dev->base_reg + HW_OFFS_OCS_ECC_CX_DATA_OUT, in ocs_ecc_read_cx_out()
199 memcpy_fromio(cy_out, dev->base_reg + HW_OFFS_OCS_ECC_CY_DATA_OUT, in ocs_ecc_read_cy_out()
867 status = ioread32(ecc_dev->base_reg + HW_OFFS_OCS_ECC_ISR); in ocs_ecc_irq_handler()
[all …]
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_coresight.c1955 const u64 base_reg) in gaudi2_unlock_coresight_unit() argument
1959 WREG32(base_reg + mmCORESIGHT_UNLOCK_REGISTER_OFFSET, CORESIGHT_UNLOCK); in gaudi2_unlock_coresight_unit()
1961 rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET, in gaudi2_unlock_coresight_unit()
1967 base_reg); in gaudi2_unlock_coresight_unit()
1975 u64 base_reg; in gaudi2_config_stm() local
1985 base_reg = debug_stm_regs[params->reg_idx]; in gaudi2_config_stm()
1990 if (!base_reg) in gaudi2_config_stm()
1997 read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET); in gaudi2_config_stm()
2001 rc = gaudi2_unlock_coresight_unit(hdev, base_reg); in gaudi2_config_stm()
2011 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x80004); in gaudi2_config_stm()
[all …]
/openbmc/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-blkctl.c26 void __iomem *base_reg; member
32 dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
35 blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
38 blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL); in dcss_blkctl_cfg()
49 blkctl->base_reg = ioremap(blkctl_base, SZ_4K); in dcss_blkctl_init()
50 if (!blkctl->base_reg) { in dcss_blkctl_init()
66 if (blkctl->base_reg) in dcss_blkctl_exit()
67 iounmap(blkctl->base_reg); in dcss_blkctl_exit()
H A Ddcss-dtg.c80 void __iomem *base_reg; member
101 dcss_writel(val, dtg->base_reg + ofs); in dcss_dtg_write()
112 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS); in dcss_dtg_irq_handler()
119 dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_irq_handler()
134 dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_irq_config()
163 dtg->base_reg = ioremap(dtg_base, SZ_4K); in dcss_dtg_init()
164 if (!dtg->base_reg) { in dcss_dtg_init()
185 iounmap(dtg->base_reg); in dcss_dtg_init()
197 if (dtg->base_reg) in dcss_dtg_exit()
198 iounmap(dtg->base_reg); in dcss_dtg_exit()
[all …]
H A Ddcss-ss.c64 void __iomem *base_reg; member
76 dcss_writel(val, ss->base_reg + ofs); in dcss_ss_write()
94 ss->base_reg = ioremap(ss_base, SZ_4K); in dcss_ss_init()
95 if (!ss->base_reg) { in dcss_ss_init()
110 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_exit()
112 if (ss->base_reg) in dcss_ss_exit()
113 iounmap(ss->base_reg); in dcss_ss_exit()
178 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_shutoff()
H A Ddcss-dpr.c93 void __iomem *base_reg; member
138 ch->base_reg = ioremap(ch->base_ofs, SZ_4K); in dcss_dpr_ch_init_all()
139 if (!ch->base_reg) { in dcss_dpr_ch_init_all()
148 dcss_writel(0xff, ch->base_reg + DCSS_DPR_IRQ_MASK); in dcss_dpr_ch_init_all()
171 if (dpr->ch[i].base_reg) in dcss_dpr_init()
172 iounmap(dpr->ch[i].base_reg); in dcss_dpr_init()
191 dcss_writel(0, ch->base_reg + DCSS_DPR_SYSTEM_CTRL0); in dcss_dpr_exit()
193 if (ch->base_reg) in dcss_dpr_exit()
194 iounmap(ch->base_reg); in dcss_dpr_exit()
/openbmc/linux/arch/arm/mach-omap1/
H A Dirq.c58 unsigned long base_reg; member
116 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
117 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
120 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
121 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
128 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
129 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
130 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
131 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
208 irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff); in omap1_init_irq()
/openbmc/linux/sound/soc/codecs/
H A Darizona.h168 #define ARIZONA_MUX_ENUMS(name, base_reg) \ argument
169 static ARIZONA_MUX_ENUM_DECL(name##_enum, base_reg); \
172 #define ARIZONA_MIXER_ENUMS(name, base_reg) \ argument
173 ARIZONA_MUX_ENUMS(name##_in1, base_reg); \
174 ARIZONA_MUX_ENUMS(name##_in2, base_reg + 2); \
175 ARIZONA_MUX_ENUMS(name##_in3, base_reg + 4); \
176 ARIZONA_MUX_ENUMS(name##_in4, base_reg + 6)
178 #define ARIZONA_DSP_AUX_ENUMS(name, base_reg) \ argument
179 ARIZONA_MUX_ENUMS(name##_aux1, base_reg); \
180 ARIZONA_MUX_ENUMS(name##_aux2, base_reg + 8); \
[all …]
H A Dmadera.h215 #define MADERA_MUX_ENUMS(name, base_reg) \ argument
216 static MADERA_MUX_ENUM_DECL(name##_enum, base_reg); \
219 #define MADERA_MIXER_ENUMS(name, base_reg) \ argument
220 MADERA_MUX_ENUMS(name##_in1, base_reg); \
221 MADERA_MUX_ENUMS(name##_in2, base_reg + 2); \
222 MADERA_MUX_ENUMS(name##_in3, base_reg + 4); \
223 MADERA_MUX_ENUMS(name##_in4, base_reg + 6)
225 #define MADERA_DSP_AUX_ENUMS(name, base_reg) \ argument
226 MADERA_MUX_ENUMS(name##_aux1, base_reg); \
227 MADERA_MUX_ENUMS(name##_aux2, base_reg + 8); \
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_csc.c116 u32 base_reg; in sun8i_csc_set_coefficients() local
123 base_reg = SUN8I_CSC_COEFF(base, 0); in sun8i_csc_set_coefficients()
124 regmap_bulk_write(map, base_reg, table, 12); in sun8i_csc_set_coefficients()
129 base_reg = SUN8I_CSC_COEFF(base, i + 1); in sun8i_csc_set_coefficients()
131 base_reg = SUN8I_CSC_COEFF(base, i - 1); in sun8i_csc_set_coefficients()
133 base_reg = SUN8I_CSC_COEFF(base, i); in sun8i_csc_set_coefficients()
134 regmap_write(map, base_reg, table[i]); in sun8i_csc_set_coefficients()
/openbmc/linux/drivers/watchdog/
H A Drdc321x_wdt.c51 int base_reg; member
67 rdc321x_wdt_device.base_reg, &val); in rdc321x_wdt_trigger()
70 rdc321x_wdt_device.base_reg, val); in rdc321x_wdt_trigger()
99 rdc321x_wdt_device.base_reg, RDC_CLS_TMR); in rdc321x_wdt_start()
103 rdc321x_wdt_device.base_reg, in rdc321x_wdt_start()
159 rdc321x_wdt_device.base_reg, &value); in rdc321x_wdt_ioctl()
233 rdc321x_wdt_device.base_reg = r->start; in rdc321x_wdt_probe()
247 rdc321x_wdt_device.base_reg, RDC_WDT_RST); in rdc321x_wdt_probe()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c590 u32 base_reg, misc_reg; in clock_set_rate() local
596 base_reg = readl(&pll->pll_base); in clock_set_rate()
599 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); in clock_set_rate()
600 base_reg |= m << pllinfo->m_shift; in clock_set_rate()
602 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); in clock_set_rate()
603 base_reg |= n << pllinfo->n_shift; in clock_set_rate()
605 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift); in clock_set_rate()
606 base_reg |= p << pllinfo->p_shift; in clock_set_rate()
613 if (base_reg & PLL_BASE_OVRRIDE_MASK) { in clock_set_rate()
614 base_reg |= PLL_ENABLE_MASK; in clock_set_rate()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-en7523.c29 u32 base_reg; member
62 .base_reg = REG_GSW_CLK_DIV_SEL,
76 .base_reg = REG_EMI_CLK_DIV_SEL,
90 .base_reg = REG_BUS_CLK_DIV_SEL,
104 .base_reg = REG_SPI_CLK_FREQ_SEL,
119 .base_reg = REG_SPI_CLK_DIV_SEL,
131 .base_reg = REG_NPU_CLK_DIV_SEL,
145 .base_reg = REG_CRYPTO_CLKSRC,
166 val = readl(base + desc->base_reg); in en7523_get_base_rate()
184 reg = desc->div_reg ? desc->div_reg : desc->base_reg; in en7523_get_div()
/openbmc/u-boot/drivers/pinctrl/broadcom/
H A Dpinctrl-bcm283x.c26 u32 *base_reg; member
41 clrsetbits_le32(&priv->base_reg[reg_offset], in bcm2835_gpio_set_func_id()
51 val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]); in bcm2835_gpio_get_func_id()
117 priv->base_reg = dev_read_addr_ptr(dev); in bcm283x_pinctl_probe()
118 if (priv->base_reg == (void *)FDT_ADDR_T_NONE) { in bcm283x_pinctl_probe()
/openbmc/u-boot/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.c48 clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG, in mvebu_pinctl_emmc_set_mux()
55 clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG, in mvebu_pinctl_emmc_set_mux()
113 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state()
174 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state_all()
194 priv->base_reg = devfdt_get_addr_ptr(dev); in mvebu_pinctl_probe()
195 if (priv->base_reg == (void *)FDT_ADDR_T_NONE) { in mvebu_pinctl_probe()
/openbmc/linux/drivers/media/dvb-frontends/
H A Ddibx000_common.c82 while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0) in dibx000_is_i2c_done()
105 dibx000_read_word(mst, mst->base_reg + 2); in dibx000_master_i2c_write()
112 dibx000_write_word(mst, mst->base_reg, data); in dibx000_master_i2c_write()
129 dibx000_write_word(mst, mst->base_reg+1, da); in dibx000_master_i2c_write()
161 dibx000_write_word(mst, mst->base_reg+1, da); in dibx000_master_i2c_read()
169 da = dibx000_read_word(mst, mst->base_reg); in dibx000_master_i2c_read()
188 return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed)); in dibx000_i2c_set_speed()
204 return dibx000_write_word(mst, mst->base_reg + 4, intf); in dibx000_i2c_select_interface()
277 tx[0] = (((mst->base_reg + 1) >> 8) & 0xff); in dibx000_i2c_gate_ctrl()
278 tx[1] = ((mst->base_reg + 1) & 0xff); in dibx000_i2c_gate_ctrl()
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dmips-cm.c206 u32 base_reg; in __mips_cm_l2sync_phys_base() local
212 base_reg = read_gcr_l2_only_sync_base(); in __mips_cm_l2sync_phys_base()
213 if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN) in __mips_cm_l2sync_phys_base()
214 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE; in __mips_cm_l2sync_phys_base()
249 u32 base_reg; in mips_cm_probe() local
269 base_reg = read_gcr_base(); in mips_cm_probe()
270 if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) { in mips_cm_probe()
/openbmc/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c110 unsigned base_reg; in ep93xx_i2s_enable() local
125 base_reg = EP93XX_I2S_TX0EN; in ep93xx_i2s_enable()
127 base_reg = EP93XX_I2S_RX0EN; in ep93xx_i2s_enable()
128 ep93xx_i2s_write_reg(info, base_reg, 1); in ep93xx_i2s_enable()
140 unsigned base_reg; in ep93xx_i2s_disable() local
149 base_reg = EP93XX_I2S_TX0EN; in ep93xx_i2s_disable()
151 base_reg = EP93XX_I2S_RX0EN; in ep93xx_i2s_disable()
152 ep93xx_i2s_write_reg(info, base_reg, 0); in ep93xx_i2s_disable()
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2_scratch.c52 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_get_bit() argument
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
79 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_set_bit() argument
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
/openbmc/linux/drivers/bus/
H A Duniphier-system-bus.c118 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_check_boot_swap() local
121 is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE); in uniphier_system_bus_check_boot_swap()
136 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_set_reg() local
171 writel(val, base_reg + UNIPHIER_SBC_STRIDE * i); in uniphier_system_bus_set_reg()

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