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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-dma.dtsi33 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
34 assigned-clock-rates = <60000000>;
49 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
50 assigned-clock-rates = <60000000>;
65 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
66 assigned-clock-rates = <60000000>;
81 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
82 assigned-clock-rates = <60000000>;
93 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
94 assigned-clock-rates = <80000000>;
[all …]
H A Dimx8ulp.dtsi237 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
238 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
272 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
273 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
274 assigned-clock-rates = <48000000>;
285 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
286 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
287 assigned-clock-rates = <48000000>;
318 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
319 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
[all …]
H A Dimx8mp.dtsi733 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 assigned-clock-rates = <0>, <0>,
794 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
797 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
800 assigned-clock-rates = <800000000>,
810 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
812 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
814 assigned-clock-rates = <400000000>,
830 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
[all …]
H A Dimx8mq-mnt-reform2.dts105 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
106 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
107 assigned-clock-rates = <25000000>;
175 assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
176 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
177 /delete-property/assigned-clock-rates;
235 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
236 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
237 assigned-clock-rates = <25000000>;
274 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
[all …]
H A Dimx8mn-evk.dtsi270 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
271 assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
272 assigned-clock-rates = <24000000>;
327 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
328 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
329 assigned-clock-rates = <24576000>;
336 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
337 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
338 assigned-clock-rates = <24576000>;
350 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp.dtsi210 assigned-clock-rates = <48000000>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
223 assigned-clock-rates = <48000000>;
233 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
234 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
235 assigned-clock-rates = <48000000>;
245 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
[all …]
H A Dfsl-imx8dx.dtsi249 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
250 assigned-clock-rates = <24000000>;
265 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
266 assigned-clock-rates = <24000000>;
280 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
281 assigned-clock-rates = <24000000>;
296 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
297 assigned-clock-rates = <24000000>;
399 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
400 assigned-clock-rates = <80000000>;
[all …]
H A Dimx7s-warp.dts79 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
80 assigned-clock-rates = <884736000>;
220 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
222 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
223 assigned-clock-rates = <0>, <36864000>;
230 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
231 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
238 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
239 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
247 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
262 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
263 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
[all …]
H A Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
121 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-rates = <0>, <100000000>;
278 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
280 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281 assigned-clock-rates = <0>, <24576000>;
313 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
H A Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
H A Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
H A Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-main.dtsi67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
238 assigned-clocks = <&k3_clks 36 2>;
239 assigned-clock-parents = <&k3_clks 36 3>;
250 assigned-clocks = <&k3_clks 37 2>;
251 assigned-clock-parents = <&k3_clks 37 3>;
262 assigned-clocks = <&k3_clks 38 2>;
263 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi156 assigned-clocks = <&k3_clks 35 1>;
157 assigned-clock-parents = <&k3_clks 35 2>;
170 assigned-clocks = <&k3_clks 83 1>;
171 assigned-clock-parents = <&k3_clks 83 2>;
184 assigned-clocks = <&k3_clks 84 1>;
185 assigned-clock-parents = <&k3_clks 84 2>;
198 assigned-clocks = <&k3_clks 85 1>;
199 assigned-clock-parents = <&k3_clks 85 2>;
212 assigned-clocks = <&k3_clks 86 1>;
213 assigned-clock-parents = <&k3_clks 86 2>;
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi160 assigned-clocks = <&k3_clks 35 2>;
161 assigned-clock-parents = <&k3_clks 35 3>;
175 assigned-clocks = <&k3_clks 117 2>;
176 assigned-clock-parents = <&k3_clks 117 3>;
189 assigned-clocks = <&k3_clks 118 2>;
190 assigned-clock-parents = <&k3_clks 118 3>;
203 assigned-clocks = <&k3_clks 119 2>;
204 assigned-clock-parents = <&k3_clks 119 3>;
217 assigned-clocks = <&k3_clks 120 2>;
218 assigned-clock-parents = <&k3_clks 120 3>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi101 assigned-clocks = <&k3_clks 35 1>;
102 assigned-clock-parents = <&k3_clks 35 2>;
115 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
116 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
129 assigned-clocks = <&k3_clks 72 1>;
130 assigned-clock-parents = <&k3_clks 72 2>;
143 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
144 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
157 assigned-clocks = <&k3_clks 74 1>;
158 assigned-clock-parents = <&k3_clks 74 2>;
[all …]
H A Dk3-j7200-main.dtsi714 assigned-clocks = <&k3_clks 292 85>;
715 assigned-clock-parents = <&k3_clks 292 89>;
721 assigned-clocks = <&wiz0_pll0_refclk>;
722 assigned-clock-parents = <&k3_clks 292 85>;
729 assigned-clocks = <&wiz0_pll1_refclk>;
730 assigned-clock-parents = <&k3_clks 292 85>;
737 assigned-clocks = <&wiz0_refclk_dig>;
738 assigned-clock-parents = <&k3_clks 292 85>;
815 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
816 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi44 assigned-clocks = <&k3_clks 35 1>;
45 assigned-clock-parents = <&k3_clks 35 2>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
58 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
70 assigned-clocks = <&k3_clks 72 1>;
71 assigned-clock-parents = <&k3_clks 72 2>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
84 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
96 assigned-clocks = <&k3_clks 74 1>;
97 assigned-clock-parents = <&k3_clks 74 2>;
[all …]
H A Dk3-j721e-main.dtsi578 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
579 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
587 assigned-clocks = <&wiz0_pll0_refclk>;
588 assigned-clock-parents = <&k3_clks 292 11>;
594 assigned-clocks = <&wiz0_pll1_refclk>;
595 assigned-clock-parents = <&k3_clks 292 0>;
601 assigned-clocks = <&wiz0_refclk_dig>;
602 assigned-clock-parents = <&k3_clks 292 11>;
638 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
639 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
[all …]
H A Dk3-am62a-main.dtsi200 assigned-clocks = <&k3_clks 36 2>;
201 assigned-clock-parents = <&k3_clks 36 3>;
212 assigned-clocks = <&k3_clks 37 2>;
213 assigned-clock-parents = <&k3_clks 37 3>;
224 assigned-clocks = <&k3_clks 38 2>;
225 assigned-clock-parents = <&k3_clks 38 3>;
236 assigned-clocks = <&k3_clks 39 2>;
237 assigned-clock-parents = <&k3_clks 39 3>;
248 assigned-clocks = <&k3_clks 40 2>;
249 assigned-clock-parents = <&k3_clks 40 3>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroid-common.dtsi129 assigned-clocks = <&clock CLK_FOUT_EPLL>;
130 assigned-clock-rates = <45158401>;
134 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
140 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
143 assigned-clock-rates = <0>, <0>,
211 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
213 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
214 assigned-clock-rates = <0>, <176000000>;
219 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
221 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
/openbmc/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-clk-ccf.dtsi149 assigned-clocks = <&zynqmp_clk GEM_TSU>;
156 assigned-clocks = <&zynqmp_clk GEM_TSU>;
163 assigned-clocks = <&zynqmp_clk GEM_TSU>;
170 assigned-clocks = <&zynqmp_clk GEM_TSU>;
199 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
204 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
261 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
268 assigned-clocks = <&zynqmp_clk DP_STC_REF>,

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