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Searched refs:__raw_readl (Results 1 – 25 of 515) sorted by relevance

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/openbmc/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dpsc.c53 ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT); in psc_wait()
73 domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_get_domain_num()
106 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_state()
123 pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_set_state()
130 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
136 ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
160 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_enable_module()
178 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
204 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
208 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_reset_iso()
[all …]
H A Dddr3.c28 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
34 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
44 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
63 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
97 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
114 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); in ddr3_ecc_support_rmw()
133 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
331 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_check_ecc_int()
349 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_check_ecc_int()
352 value = __raw_readl(base + in ddr3_check_ecc_int()
[all …]
/openbmc/linux/arch/mips/loongson32/common/
H A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/openbmc/linux/arch/mips/alchemy/common/
H A Dusb.c102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
139 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
148 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
153 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ohci_control()
168 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control()
173 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control()
180 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
185 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dsmemc.c23 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()
24 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend()
25 sxcnfg = __raw_readl(SXCNFG); in pxa3xx_smemc_suspend()
26 memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_suspend()
27 csadrcfg[0] = __raw_readl(CSADRCFG0); in pxa3xx_smemc_suspend()
28 csadrcfg[1] = __raw_readl(CSADRCFG1); in pxa3xx_smemc_suspend()
29 csadrcfg[2] = __raw_readl(CSADRCFG2); in pxa3xx_smemc_suspend()
30 csadrcfg[3] = __raw_readl(CSADRCFG3); in pxa3xx_smemc_suspend()
78 unsigned long memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_get_memclkdiv()
/openbmc/linux/arch/arm/mach-s3c/
H A Dpm-gpio.c29 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
30 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
36 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
37 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
66 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save()
67 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save()
68 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); in samsung_gpio_pm_2bit_save()
123 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
124 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_2bit_resume()
194 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_4bit_save()
[all …]
/openbmc/linux/arch/sh/boards/mach-dreamcast/
H A Drtc.c39 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
40 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
42 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
43 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
71 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
72 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
74 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
75 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
/openbmc/linux/arch/mips/pci/
H A Dops-tx4927.c69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
80 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) in check_abort()
82 if (__raw_readl(&pcicptr->pcistatus) in check_abort()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
110 return __raw_readl(&pcicptr->g2pcfgdata); in icd_readl()
230 __raw_readl(&pcicptr->pciid) >> 16, in tx4927_pcic_setup()
231 __raw_readl(&pcicptr->pciid) & 0xffff, in tx4927_pcic_setup()
232 __raw_readl(&pcicptr->pciccrev) & 0xff, in tx4927_pcic_setup()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
307 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
[all …]
H A Dpci-ar724x.c60 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link()
86 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
108 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
128 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read()
197 data = __raw_readl(base + (where & ~3)); in ar724x_pci_write()
219 __raw_readl(base + (where & ~3)); in ar724x_pci_write()
238 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & in ar724x_pci_irq_handler()
239 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_handler()
261 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
265 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
[all …]
H A Dpci-alchemy.c114 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; in config_access()
157 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); in config_access()
164 status = __raw_readl(ctx->regs + PCI_REG_STATCMD); in config_access()
313 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); in alchemy_pci_suspend()
314 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; in alchemy_pci_suspend()
315 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_suspend()
316 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_suspend()
317 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_suspend()
318 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_suspend()
319 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_suspend()
[all …]
/openbmc/u-boot/drivers/video/
H A Dipu_common.c163 reg = __raw_readl(clk->enable_reg); in clk_ipu_enable()
169 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_enable()
174 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_enable()
185 reg = __raw_readl(clk->enable_reg); in clk_ipu_disable()
194 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_disable()
199 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_disable()
283 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
290 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); in ipu_pixel_clk_recalc()
372 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_enable()
381 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_disable()
[all …]
H A Dipu_disp.c140 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); in ipu_dmfc_set_wait4eot()
194 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
231 reg = __raw_readl(DI_STP_REP(di, wave_gen)); in ipu_di_sync_config()
242 reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config()
247 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_config()
255 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_clear()
283 reg = __raw_readl(DC_RL_CH(chan, event)); in ipu_dc_link_event()
386 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_csc_setup()
412 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_dp_csc_setup()
468 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_init()
[all …]
/openbmc/u-boot/drivers/rtc/
H A Dimxdi.c79 if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) in clear_write_error()
106 if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { in di_write_wait()
117 if (__raw_readl(&data.regs->dsr) & DSR_WEF) { in di_write_wait()
138 if (__raw_readl(&data.regs->dsr) & DSR_NVF) { in di_init()
153 if (__raw_readl(&data.regs->dsr) & DSR_CAF) { in di_init()
160 if (__raw_readl(&data.regs->dtcmr) == 0) { in di_init()
167 if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { in di_init()
168 rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); in di_init()
191 now = __raw_readl(&data.regs->dtcmr); in rtc_get()
/openbmc/linux/arch/mips/ath79/
H A Dclock.c105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init()
178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); in ar933x_clocks_init()
253 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); in ar934x_clocks_init()
257 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); in ar934x_clocks_init()
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
280 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_clocks_init()
284 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); in ar934x_clocks_init()
292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
[all …]
/openbmc/linux/drivers/soc/ixp4xx/
H A Dixp4xx-qmgr.c43 val = __raw_readl(&qmgr_regs->acc[queue][0]); in qmgr_get_entry()
55 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) in __qmgr_get_stat1()
62 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) in __qmgr_get_stat2()
87 return (__raw_readl(&qmgr_regs->statne_h) >> in qmgr_stat_below_low_watermark()
101 return (__raw_readl(&qmgr_regs->statf_h) >> in qmgr_stat_full()
129 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), in qmgr_set_irq()
149 en_bitmap = __raw_readl(&qmgr_regs->irqen[0]); in qmgr_irq1_a0()
153 src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]); in qmgr_irq1_a0()
154 stat = __raw_readl(&qmgr_regs->stat1[i >> 3]); in qmgr_irq1_a0()
174 req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) & in qmgr_irq2_a0()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
85 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
166 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
182 reg = __raw_readl(addr); in enable_i2c_clk()
203 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
217 div = __raw_readl(&imx_ccm->analog_pll_sys); in decode_pll()
222 div = __raw_readl(&imx_ccm->analog_pll_528); in decode_pll()
227 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); in decode_pll()
232 div = __raw_readl(&imx_ccm->analog_pll_enet); in decode_pll()
237 div = __raw_readl(&imx_ccm->analog_pll_audio); in decode_pll()
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Ddavinci_nand.c80 *(u32 *)buf = __raw_readl(nand); in nand_davinci_read_buf()
169 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ in nand_davinci_readecc()
182 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()
484 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_4bit_enable_hwecc()
492 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]); in nand_davinci_4bit_enable_hwecc()
504 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) & in nand_davinci_4bit_readecc()
626 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
642 val = __raw_readl(&davinci_emif_regs->nanderradd1); in nand_davinci_4bit_correct_data()
659 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
670 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
[all …]
/openbmc/linux/drivers/edac/
H A Dcpc925_edac.c327 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET + in cpc925_init_csrows()
329 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET + in cpc925_init_csrows()
387 apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET); in cpc925_mc_init()
394 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET); in cpc925_mc_init()
529 apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET); in cpc925_mc_check()
533 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET); in cpc925_mc_check()
536 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET); in cpc925_mc_check()
560 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET)); in cpc925_mc_check()
564 __raw_readl(pdata->vbase + REG_MSCR_OFFSET)); in cpc925_mc_check()
566 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET)); in cpc925_mc_check()
[all …]
/openbmc/linux/arch/mips/ralink/
H A Dmt7621.c71 if (__raw_readl(dm) != __raw_readl(dm + size)) in mt7621_addr_wraparound_test()
74 return __raw_readl(dm) == __raw_readl(dm + size); in mt7621_addr_wraparound_test()
94 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0); in mt7621_get_soc_name0()
99 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1); in mt7621_get_soc_name1()
121 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV); in mt7621_get_soc_rev()
/openbmc/linux/drivers/irqchip/
H A Dirq-ath79-misc.c41 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & in ath79_misc_irq_handler()
42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler()
66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
83 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
92 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); in ar724x_misc_irq_ack()
96 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); in ar724x_misc_irq_ack()
/openbmc/linux/drivers/char/hw_random/
H A Dmxc-rnga.c68 int level = (__raw_readl(mxc_rng->mem + RNGA_STATUS) & in mxc_rnga_data_present()
84 *data = __raw_readl(mxc_rng->mem + RNGA_OUTPUT_FIFO); in mxc_rnga_data_read()
87 err = __raw_readl(mxc_rng->mem + RNGA_STATUS) & RNGA_STATUS_ERROR_INT; in mxc_rnga_data_read()
92 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_data_read()
106 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
110 osc = __raw_readl(mxc_rng->mem + RNGA_STATUS); in mxc_rnga_init()
117 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
128 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_cleanup()
/openbmc/linux/arch/arm/mach-davinci/
H A Dpm.c50 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
57 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
63 val = __raw_readl(pm_config.deepsleep_reg); in davinci_pm_suspend()
74 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
79 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
87 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
95 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
/openbmc/u-boot/post/cpu/mpc83xx/
H A Decc.c62 if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) { in ecc_post_test()
110 if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) || in ecc_post_test()
111 (__raw_readl(&ddr->data_err_inject_hi) != in ecc_post_test()
112 (__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) || in ecc_post_test()
113 (__raw_readl(&ddr->data_err_inject_lo) != in ecc_post_test()
114 (__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) { in ecc_post_test()
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dubc.c50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
69 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) in sh4a_ubc_active_mask()
77 return __raw_readl(UBC_CCMFR); in sh4a_ubc_triggered_mask()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
121 (void)__raw_readl(UBC_CRR(i)); in sh4a_ubc_init()

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