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Searched refs:XCHAL_ICACHE_SIZE (Results 1 – 25 of 27) sorted by relevance

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/openbmc/u-boot/arch/xtensa/include/asm/
H A Dcacheasm.h16 #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
92 #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
93 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
129 #if XCHAL_ICACHE_SIZE
167 #if XCHAL_ICACHE_SIZE
204 #if XCHAL_ICACHE_SIZE
/openbmc/linux/arch/xtensa/include/asm/
H A Dcacheasm.h95 #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
96 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
135 #if XCHAL_ICACHE_SIZE
136 __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
173 #if XCHAL_ICACHE_SIZE
210 #if XCHAL_ICACHE_SIZE
H A Dcache.h21 #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_cache.S29 #ifdef XCHAL_ICACHE_SIZE
90 #if XCHAL_ICACHE_SIZE
124 #if XCHAL_ICACHE_SIZE
126 movi a3, XCHAL_ICACHE_SIZE
/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h119 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h121 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h134 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h161 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h154 #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h125 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h126 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h185 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h124 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/
H A Doverlay_tool.h140 XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
475 (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h164 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h143 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h165 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h185 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h213 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h213 #define XCHAL_ICACHE_SIZE 65536 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h213 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h191 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h214 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h222 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h236 #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ macro

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