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Searched refs:XCHAL_HAVE_XLT_CACHEATTR (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h343 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h345 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h368 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h437 #define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h456 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h407 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h408 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h457 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h406 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/
H A Doverlay_tool.h152 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
378 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h458 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h437 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h459 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h516 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h580 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h559 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h558 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h558 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h559 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h594 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h615 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h697 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro