| /openbmc/linux/arch/xtensa/variants/fsf/include/variant/ |
| H A D | core.h | 341 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-fsf/ |
| H A D | core-isa.h | 343 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| H A D | core.h | 366 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-dsp3400/ |
| H A D | core-isa.h | 435 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-lx106/ |
| H A D | core-isa.h | 454 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | core-isa.h | 405 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/linux/arch/xtensa/variants/dc232b/include/variant/ |
| H A D | core.h | 406 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | core-isa.h | 455 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/ |
| H A D | core.h | 404 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | core-isa.h | 456 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/ |
| H A D | core.h | 435 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | core.h | 457 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | core.h | 514 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | core.h | 578 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | core.h | 557 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | core-isa.h | 556 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | core.h | 556 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | core.h | 557 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | core-isa.h | 592 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | core-isa.h | 613 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-isa.h | 695 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
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| /openbmc/qemu/target/xtensa/ |
| H A D | overlay_tool.h | 156 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
|