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Searched refs:TRANSCONF (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c66 if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled()
82 if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled()
190 vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &= in emulate_monitor_status_change()
251 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
252 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; in emulate_monitor_status_change()
509 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
H A Dhandlers.c2270 MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2271 MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2272 MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2273 MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_pch_display.c273 pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe)); in ilk_enable_pch_transcoder()
415 u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5; in ilk_pch_enable()
559 pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
H A Dintel_crt.c724 u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); in intel_crt_load_detect()
726 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), in intel_crt_load_detect()
728 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); in intel_crt_load_detect()
737 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf); in intel_crt_load_detect()
H A Dintel_display.c295 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), in intel_wait_for_pipe_off()
317 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); in assert_transcoder()
431 reg = TRANSCONF(cpu_transcoder); in intel_enable_transcoder()
470 reg = TRANSCONF(cpu_transcoder); in intel_disable_transcoder()
2598 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; in intel_pipe_is_interlaced()
2600 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; in intel_pipe_is_interlaced()
2749 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); in i9xx_set_pipeconf()
2750 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); in i9xx_set_pipeconf()
2911 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); in i9xx_get_pipe_config()
3079 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); in ilk_set_pipeconf()
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H A Dintel_fdi.c904 temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_pll_enable()
960 temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_disable()
986 temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_disable()
H A Dicl_dsi.c1012 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE); in gen11_dsi_enable_transcoder()
1015 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans), in gen11_dsi_enable_transcoder()
1278 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0); in gen11_dsi_disable_transcoder()
1281 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans), in gen11_dsi_disable_transcoder()
1714 tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans)); in gen11_dsi_get_hw_state()
H A Dintel_drrs.c78 intel_de_rmw(dev_priv, TRANSCONF(cpu_transcoder), in intel_drrs_set_refresh_rate_pipeconf()
H A Dintel_display_power_well.c1045 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1047 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1061 return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1062 intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
H A Dvlv_dsi.c968 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c125 MMIO_D(TRANSCONF(TRANSCODER_A)); in iterate_generic_mmio()
126 MMIO_D(TRANSCONF(TRANSCODER_B)); in iterate_generic_mmio()
127 MMIO_D(TRANSCONF(TRANSCODER_C)); in iterate_generic_mmio()
128 MMIO_D(TRANSCONF(TRANSCODER_EDP)); in iterate_generic_mmio()
H A Di915_reg.h2642 #define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF) macro