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Searched refs:TIMING_CFG2_ADD_LAT_SHIFT (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/include/configs/km/
H A Dkm8321-common.h112 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
H A Dkm8309-common.h148 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
/openbmc/u-boot/include/configs/
H A Dkm8360.h137 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
H A Dmpc8308_p1m.h162 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A DMPC8308RDB.h158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A DMPC8323ERDB.h108 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A Dids8313.h129 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
H A Dve8313.h84 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A DMPC832XEMDS.h118 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A DMPC8315ERDB.h133 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A Dhrcon.h149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A DMPC8313ERDB.h145 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A DMPC837XERDB.h171 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A DMPC837XEMDS.h158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
H A Dstrider.h149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
/openbmc/u-boot/drivers/ram/
H A Dmpc83xx_sdram.c55 static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3); variable
777 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT | in mpc83xx_sdram_probe()
/openbmc/u-boot/include/
H A Dmpc83xx.h1214 #define TIMING_CFG2_ADD_LAT_SHIFT 28 macro