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Searched refs:TIMING_CFG0_RWT_SHIFT (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/include/configs/km/
H A Dkm8321-common.h96 (0 << TIMING_CFG0_RWT_SHIFT))
H A Dkm8309-common.h132 (0 << TIMING_CFG0_RWT_SHIFT))
/openbmc/u-boot/include/configs/
H A Dkm8360.h119 (0 << TIMING_CFG0_RWT_SHIFT))
H A Dmpc8308_p1m.h144 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A DMPC8308RDB.h140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A DMPC8323ERDB.h90 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A Dids8313.h113 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
H A Dve8313.h66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A DMPC832XEMDS.h100 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A DMPC8315ERDB.h115 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A Dhrcon.h131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A DMPC8313ERDB.h127 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A DMPC837XERDB.h153 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A DMPC837XEMDS.h140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
H A Dstrider.h131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
/openbmc/u-boot/drivers/ram/
H A Dmpc83xx_sdram.c33 static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1); variable
585 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT | in mpc83xx_sdram_probe()
/openbmc/u-boot/include/
H A Dmpc83xx.h1159 #define TIMING_CFG0_RWT_SHIFT 30 macro