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Searched refs:TCG_COND_GT (Results 1 – 25 of 42) sorted by relevance

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/openbmc/qemu/target/hexagon/
H A Dgen_tcg.h685 tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \
778 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
780 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
782 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
784 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
786 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
788 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
790 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
792 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
829 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
[all …]
H A Dgen_tcg_hvx.h433 fGEN_TCG_VEC_CMP(TCG_COND_GT, MO_32, 4)
435 fGEN_TCG_VEC_CMP(TCG_COND_GT, MO_16, 2)
437 fGEN_TCG_VEC_CMP(TCG_COND_GT, MO_8, 1)
464 fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_and)
466 fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_or)
468 fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_xor)
478 fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_and)
480 fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_or)
482 fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_xor)
492 fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_and)
[all …]
H A Dgenptr.c1170 tcg_gen_brcondi_tl(TCG_COND_GT, shift_amt32, 63, zero); in gen_asr_r_svw_trun()
/openbmc/qemu/include/tcg/
H A Dtcg-cond.h52 TCG_COND_GT = 0 | 4 | 2 | 0, enumerator
/openbmc/qemu/target/alpha/
H A Dtranslate.c501 case TCG_COND_GT: in gen_fold_mzero()
1731 tcg_gen_movcond_i64(TCG_COND_GT, vc, va, load_zero(ctx), in translate_one()
2271 gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc); in translate_one()
2815 ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21); in translate_one()
2847 ret = gen_bcond(ctx, TCG_COND_GT, ra, disp21); in translate_one()
/openbmc/qemu/tcg/
H A Dtci.c217 case TCG_COND_GT: in tci_compare32()
265 case TCG_COND_GT: in tci_compare64()
1052 [TCG_COND_GT] = "gt", in str_c()
H A Doptimize.c625 case TCG_COND_GT: in do_constant_folding_cond_32()
659 case TCG_COND_GT: in do_constant_folding_cond_64()
683 case TCG_COND_GT: in do_constant_folding_cond_eq()
H A Dtcg-op-vec.c662 do_minmax(vece, r, a, b, INDEX_op_smax_vec, TCG_COND_GT); in tcg_gen_smax_vec()
/openbmc/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc760 tcg_gen_cmp_vec(TCG_COND_GT, vece, t2, t0, t1);
986 tcg_gen_movcond_i64(TCG_COND_GT, t0, b, e, ones, zero);
1182 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
1183 TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
1184 TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
1185 TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1299 tcg_gen_negsetcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1);
1333 tcg_gen_brcond_i64((sign ? TCG_COND_GT : TCG_COND_GTU), vra, vrb, gt);
/openbmc/qemu/target/mips/tcg/
H A Dmxu_translate.c3834 tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi); in gen_mxu_Q16SAT()
3846 tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo); in gen_mxu_Q16SAT()
3870 tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi); in gen_mxu_Q16SAT()
3882 tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo); in gen_mxu_Q16SAT()
3935 tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_b_hi_gt); in gen_mxu_q16scop()
3957 tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_c_hi_gt); in gen_mxu_q16scop()
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc314 case TCG_COND_GT:
731 [TCG_COND_GT] = BC | BI(0, CR_GT) | BO_COND_TRUE,
747 [TCG_COND_GT] = ISEL | BC_(0, CR_GT),
1824 case TCG_COND_GT:
2045 case TCG_COND_GT:
2181 [TCG_COND_GT ] = { CR_GT, CR_GT },
2230 case TCG_COND_GT:
3773 case TCG_COND_GT:
3814 case TCG_COND_GT:
/openbmc/qemu/target/hexagon/idef-parser/
H A Didef-parser.y628 $$ = gen_bin_cmp(c, &@1, TCG_COND_GT, &$1, &$3);
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc423 [TCG_COND_GT] = S390_CC_GT,
441 [TCG_COND_GT] = S390_CC_GT,
590 case TCG_COND_GT:
1325 case TCG_COND_GT:
1410 case TCG_COND_GT:
2864 case TCG_COND_GT:
2898 case TCG_COND_GT:
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc546 [TCG_COND_GT] = JCC_JG,
1650 case TCG_COND_GT:
1651 tcg_out_brcond(s, 0, TCG_COND_GT, args[1], args[3], const_args[3],
1658 tcg_out_brcond(s, 0, TCG_COND_GT, args[1], args[3], const_args[3],
3100 [TCG_COND_GT] = 0,
3140 case TCG_COND_GT:
3173 [TCG_COND_GT] = 6,
3213 && cond != TCG_COND_GT) {
4051 tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1,
/openbmc/qemu/target/openrisc/
H A Dtranslate.c981 tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, in trans_l_sfgts()
1045 tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); in trans_l_sfgtsi()
/openbmc/qemu/target/tricore/
H A Dtranslate.c505 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
1006 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1215 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1750 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
2137 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); in gen_absdif()
2142 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); in gen_absdif()
2517 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); in gen_shaci()
2972 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
5113 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, in decode_rc_accumulator()
5734 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc366 [TCG_COND_GT] = COND_GT,
2521 [TCG_COND_GT] = I3616_CMGT,
2528 [TCG_COND_GT] = I3611_CMGT,
2535 [TCG_COND_GT] = I3617_CMGT0,
2542 [TCG_COND_GT] = I3612_CMGT0,
/openbmc/qemu/target/sh4/
H A Dtranslate.c733 tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
1350 tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc246 [TCG_COND_GT] = COND_GT,
1267 case TCG_COND_GT:
2590 [TCG_COND_GT] = INSN_VCGT,
2598 [TCG_COND_GT] = INSN_VCGT0,
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc354 [TCG_COND_GT] = { OPC_VMSLT_VV, true },
370 [TCG_COND_GT] = { OPC_VMSGT_VI, -16, 15, false },
1193 [TCG_COND_GT] = { OPC_BLT, true },
1230 case TCG_COND_GT: /* -> LE */
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.c.inc618 [TCG_COND_GT] = COND_G,
629 [TCG_COND_GT] = RCOND_GZ,
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc911 case TCG_COND_GT:
959 [TCG_COND_GT] = OPC_BGTZ,
974 case TCG_COND_GT:
/openbmc/qemu/target/arm/tcg/
H A Dgengvec.c87 GEN_CMP0(gen_gvec_cgt0, TCG_COND_GT) in GEN_CMP0()
1207 tcg_gen_cmpsel_vec(TCG_COND_GT, vece, lval, lsh, max, zero, lval); in gen_sshl_vec()
/openbmc/qemu/target/s390x/tcg/
H A Dtranslate.c657 TCG_COND_GT, TCG_COND_GT, /* | | GT | x */
1573 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT); in op_bx32()
1596 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT); in op_bx64()
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc572 case TCG_COND_GT: /* -> LE */
722 [TCG_COND_GT] = { OPC_BGT, false },

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