Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0 |
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4977ce19 |
| 01-May-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-tcg-20240501' of https://gitlab.com/rth7680/qemu into staging
plugins: Rewrite plugin tcg expansion
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FA
Merge tag 'pull-tcg-20240501' of https://gitlab.com/rth7680/qemu into staging
plugins: Rewrite plugin tcg expansion
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmYyUpkdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV98VAgAoTqIWPHtPJOS800G # TlFuQjkEzQCPSKAh6ZbotsAMvfNwBloPpdrUlFr/jT7mURjEl2B7UC/4LzdhuGeQ # U/xZt5rXsYvyfS3VwLf8pKBIscF7XjJ1rdfYMvBg9XaNp5VV0aEIk3+6P0uYtzXG # cREF0uCYfdK6uoiuifhqRAkgrNnamdwpPbbfvzDQI13wICW7SfR7dcd629clVZ1O # QvD1M4bpTWyhClbZzaoHqyPs+HQEM/AY0wOTfYZNbQBu6zFZXNDZCvYhIEWonPBO # AKe5KWUrQMwLJhRVejaSSZZDjMdcz3HLaGJppP89/WB+gpY09+LsiuqT7k5c12Bw # ueLEhw== # =mn63 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 May 2024 07:32:57 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20240501' of https://gitlab.com/rth7680/qemu: plugins: Update the documentation block for plugin-gen.c plugins: Inline plugin_gen_empty_callback plugins: Merge qemu_plugin_tb_insn_get to plugin-gen.c plugins: Split out common cb expanders plugins: Replace pr_ops with a proper debug dump flag plugins: Introduce PLUGIN_CB_MEM_REGULAR plugins: Simplify callback queues tcg: Remove INDEX_op_plugin_cb_{start,end} tcg: Remove TCG_CALL_PLUGIN plugins: Remove plugin helpers plugins: Use emit_before_op for PLUGIN_GEN_FROM_MEM plugins: Use emit_before_op for PLUGIN_GEN_FROM_INSN plugins: Add PLUGIN_GEN_AFTER_TB plugins: Use emit_before_op for PLUGIN_GEN_FROM_TB plugins: Use emit_before_op for PLUGIN_GEN_AFTER_INSN plugins: Create TCGHelperInfo for all out-of-line callbacks plugins: Move function pointer in qemu_plugin_dyn_cb plugins: Zero new qemu_plugin_dyn_cb entries tcg: Pass function pointer to tcg_gen_call* tcg: Make tcg/helper-info.h self-contained
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ed30e7b1 |
| 14-Mar-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Make tcg/helper-info.h self-contained
Move MAX_CALL_IARGS from tcg.h and include for the define of TCG_TARGET_REG_BITS.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe
tcg: Make tcg/helper-info.h self-contained
Move MAX_CALL_IARGS from tcg.h and include for the define of TCG_TARGET_REG_BITS.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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03e4bc0b |
| 08-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging
tcg: Introduce TCG_COND_TST{EQ,NE} target/alpha: Use TCG_COND_TST{EQ,NE} target/m68k: Use TCG_COND_TST{EQ,NE} in gen_f
Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging
tcg: Introduce TCG_COND_TST{EQ,NE} target/alpha: Use TCG_COND_TST{EQ,NE} target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} target/s390x: Improve general case of disas_jcc
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmXBpTAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/p6gf9HAasTSRECk2cvjW9 # /mcJy0AIaespnI50fG8fm48OoFl0847CdrsJycpZ1spw3W3Wb0cVbMbq/teNMjXZ # 0SGQJFk9Baq7wMhW7VzhSzJ96pcorpQprp7XBMdheLXqpT4zsM/EuwEAepBk8RUG # 3kCeo38dswXE681ZafZkd/8pPzII19sQK8eiMpceeYkBsbbep+DDcnE18Ee4kISS # u0SbuslKVahxd86LKuzrcz0pNFcmFuR5jRP9hmbQ0MfeAn0Pxlndi+ayZNghfgPf # 3hDjskiionFwxb/OoRj45BssTWfDiluWl7IUsHfegPXCQ2Y+woT5Vq6TVGZn0GqS # c6RLQQ== # =TMiE # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 Feb 2024 03:19:12 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu: (39 commits) tcg/tci: Support TCG_COND_TST{EQ,NE} tcg/s390x: Support TCG_COND_TST{EQ,NE} tcg/s390x: Add TCG_CT_CONST_CMP tcg/s390x: Split constraint A into J+U tcg/ppc: Support TCG_COND_TST{EQ,NE} tcg/ppc: Add TCG_CT_CONST_CMP tcg/ppc: Tidy up tcg_target_const_match tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc tcg/sparc64: Support TCG_COND_TST{EQ,NE} tcg/sparc64: Pass TCGCond to tcg_out_cmp tcg/sparc64: Hoist read of tcg_cond_to_rcond tcg/i386: Use TEST r,r to test 8/16/32 bits tcg/i386: Improve TSTNE/TESTEQ vs powers of two tcg/i386: Support TCG_COND_TST{EQ,NE} tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp tcg/i386: Pass x86 condition codes to tcg_out_cmov tcg/arm: Support TCG_COND_TST{EQ,NE} tcg/arm: Split out tcg_out_cmp() tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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23c5692a |
| 25-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/tci: Support TCG_COND_TST{EQ,NE}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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74949263 |
| 06-Nov-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu into staging
util: Add cpuinfo for loongarch64 tcg/loongarch64: Use cpuinfo.h tcg/loongarch64: Improve register allocation for INDEX_
Merge tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu into staging
util: Add cpuinfo for loongarch64 tcg/loongarch64: Use cpuinfo.h tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128 host/include/loongarch64: Add atomic16 load and store tcg: Move expanders out of line tcg/mips: Always implement movcond tcg/mips: Implement neg opcodes tcg/loongarch64: Implement neg opcodes tcg: Make movcond and neg required opcodes tcg: Optimize env memory operations tcg: Canonicalize sub of immediate to add tcg/sparc64: Implement tcg_out_extrl_i64_i32
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVJpT0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9i7QgAtjxUB3y/caCPp0Me # 3cXYtpL1vNxx+cTESGMlmIRSji+cEOxYSpnY0itxXcKpcwP8Au8eoTe85NxyIllg # 2R/SA2jlmrmiipI+bwb0UBCy+BzUfMgmegA88K2W22J0fetwIy19PN9ORmYdLiYE # /pWNFOSPzhYEJgOw7V2MwciUv3llolMOfxU7VT4oVaCknZRsyaGUwl4uTT4GdPuK # p29O9nziyKDmNTqJ9SKKll5bzwCMAgkn2lUcMGf+rpl7ZxjgvysUYrGXKmOnj4Uu # eCU2d3ZHoSspcYEjbFASlyPd7z5apGI8Iq2K35FUhURFPv06Su/bIGOOD4ujP2Qp # vc/bFQ== # =Mvaf # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 10:47:25 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu: (35 commits) tcg/sparc64: Implement tcg_out_extrl_i64_i32 tcg/optimize: Canonicalize sub2 with constants to add2 tcg/optimize: Canonicalize subi to addi during optimization tcg: Canonicalize subi to addi during opcode generation tcg/optimize: Split out arg_new_constant tcg: Eliminate duplicate env store operations tcg/optimize: Optimize env memory operations tcg/optimize: Split out cmp_better_copy tcg/optimize: Pipe OptContext into reset_ts tcg: Don't free vector results tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} tcg/loongarch64: Implement neg opcodes tcg/mips: Implement neg opcodes tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} tcg/mips: Always implement movcond tcg/mips: Split out tcg_out_setcond_int tcg: Move tcg_temp_free_* out of line tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line tcg: Move tcg_constant_* out of line tcg: Unexport tcg_gen_op*_{i32,i64} ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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b701f195 |
| 25-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
The movcond opcode is now mandatory for backends to implement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
The movcond opcode is now mandatory for backends to implement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
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c102e297 |
| 07-Jun-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-ci-20230607' of https://gitlab.com/rth7680/qemu into staging
Fix TCI regressions vs Int128 Fix Arm build vs --disable-tcg Fix iotest 194.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAA
Merge tag 'pull-ci-20230607' of https://gitlab.com/rth7680/qemu into staging
Fix TCI regressions vs Int128 Fix Arm build vs --disable-tcg Fix iotest 194.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSApKodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/0mAf/f6+JI3tF+CxyWs+J # 5LSDn8hosJefuy+jkhSM/aPIlX5gYvmoA7S/XNGrDG0+yNS5SriZKuyt9hB/gZ5D # JFred7xuI0RmkEX3cnqFgsrtFmOYdx6G5tt4MU25uzKFyPgYg+6hsF0fotcFCPIp # s2XIjEc7X1hk/xr4LRRxJeRrK+ZK48sN+K9HzITclKB3v11Dxv/a0OT2kdrPvlvb # d/yNYewZrxM86vFmlIR/dT+M/qq7ULonlnH1HuWh8IaPO0owEyJPZPFw07C3ivUi # uIplMcqk/2Um1R8zwUgaByINB3uVQXp1PyYsbjxvS34mdLwtYXF8b+/5Ma6tc3Tb # sWkIXg== # =NNK9 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 07 Jun 2023 08:39:22 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-ci-20230607' of https://gitlab.com/rth7680/qemu: iotests: fix 194: filter out racy postcopy-active event gitlab: Add cross-arm64-kvm-only target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG tcg/tci: Adjust call-clobbered regs for int128_t tcg/tci: Adjust passing of MemOpIdx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ab64da79 |
| 06-Jun-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/tci: Adjust passing of MemOpIdx
Since adding MO_ATOM_MASK, the maximum MemOpIdx requires 15 bits, which overflows the 12 bit field allocated for TCI memory ops. Expand the field to 16 bits for 2
tcg/tci: Adjust passing of MemOpIdx
Since adding MO_ATOM_MASK, the maximum MemOpIdx requires 15 bits, which overflows the 12 bit field allocated for TCI memory ops. Expand the field to 16 bits for 2-operand memory ops, and place the value in TCG_REG_TMP for 3-operand memory ops (same as we already do for 4-operand memory ops).
Cures a debug assert for aarch64, with FEAT_LSE2 enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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369081c4 |
| 05-Jun-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging
Build tcg/ once for system and once for user. Unmap perf_marker. Remove left over _link_error() definitions.
# -----BEG
Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging
Build tcg/ once for system and once for user. Unmap perf_marker. Remove left over _link_error() definitions.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmR+QekdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8NJwf+PE6ShfN+N65hwt0w # mgIrWNadgnXezEyaUdEuzLre9Ln9uD9Are948xIGPTVoLyr2wEr+Ma9dFI+GpTHY # 8C0b5v0SfHBBIK+wJb7VNcEdssRXVTcpikmmYv9IRpFTT8349bCdvJhuwojU5cyx # NGgq9ydJ/dEUDtmVU6EnOyLCDSHg2mc+KPVWhjXaVbVPTyP6Xmb0BwSSUt1t5NQK # Zw7E6G4z7QYXa7GNPTtXSWzTH3y9bSLQNj3jzHfJ6DPW23zxhFjCPhJYl1ecOHVF # pxXEEIjieHQxdlm3kg+tcCoZSJ6OXESNzu2D8zk8Kf6xJjMItTQOOuokWM6mBX4y # VbQoXg== # =8vrl # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 Jun 2023 01:13:29 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu: (52 commits) tcg/tcg-op-vec: Remove left over _link_error() definitions accel/tcg: Unmap perf_marker tcg: Build once for system and once for user-only exec/poison: Do not poison CONFIG_SOFTMMU plugins: Drop unused headers from exec/plugin-gen.h plugins: Move plugin_insn_append to translator.c tcg: Remove target-specific headers from tcg.[ch] tcg: Move env defines out of NEED_CPU_H in helper-head.h tcg: Fix PAGE/PROT confusion accel/tcg: Tidy includes for translator.[ch] target/arm: Add missing include of exec/exec-all.h target/*: Add missing includes of exec/translation-block.h target/mips: Tidy helpers for translation target/arm: Tidy helpers for translation accel/tcg: Move translator_fake_ldb out of line target/ppc: Inline gen_icount_io_start() accel/tcg: Introduce translator_io_start accel/tcg: Move most of gen-icount.h into translator.c include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE tcg: Spit out exec/translation-block.h ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0 |
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ad3d0e4d |
| 28-Mar-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h
Create tcg/tcg-op-common.h, moving everything that does not concern TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header instead of tcg-op
tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h
Create tcg/tcg-op-common.h, moving everything that does not concern TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header instead of tcg-op.h, in preparation for compiling tcg/ only once.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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6972ef14 |
| 16-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu into staging
tcg/i386: Fix tcg_out_addi_ptr for win64 tcg: Implement atomicity for TCGv_i128 tcg: First quarter of cleanups for bui
Merge tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu into staging
tcg/i386: Fix tcg_out_addi_ptr for win64 tcg: Implement atomicity for TCGv_i128 tcg: First quarter of cleanups for building tcg once
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRkWC8dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/I+wf8CUF+J/E9u0EuurrB # 1asDicANUJIACnqlcEpSPKuSMtbzo1RDTQUR+d3GWJjyLASvSJZFZTQqWBdACRpc # sNuDz3/1a6FbiM14CwIVmPpcjQXa+18Ck670Chmw51KyEt2xyDJTySFIGEqjiuTf # YVDBbOs8neFZdcDvAs1qNUTjhRj4nNtkpQoBpv0tGH7E0CzPp6OcvxwfieVyLOIa # Cy1ELM3aMyVN5MTjnORYLK70Pa9emdjB88SlypZx363ARKC7B50lzYPQ4E5zrOZq # FKrOq5nFWLCtn4BID0R+jUmuUP6znR/hTlToDmf/9B4j9TUivERWlc54lz3YU6Gn # su3FKg== # =LVOb # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 May 2023 09:29:35 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu: (74 commits) tcg: Split out exec/user/guest-base.h tcg: Add tlb_dyn_max_bits to TCGContext tcg: Add page_bits and page_mask to TCGContext tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/aarch64: Remove USE_GUEST_BASE tcg/arm: Remove TARGET_LONG_BITS tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/i386: Adjust type of tlb_mask tcg/i386: Conditionalize tcg_out_extu_i32_i64 tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32 tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong tcg: Split INDEX_op_qemu_{ld,st}* for guest address size tcg: Remove TCGv from tcg_gen_atomic_* tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_* tcg: Add addr_type to TCGContext accel/tcg: Widen plugin_gen_empty_mem_callback to i64 tcg: Reduce copies for plugin_gen_mem_callbacks ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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dd7dc93e |
| 20-Mar-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
We now have the address size as part of the opcode, so we no longer need to test TARGET_LONG_BITS. We can use uint64_t for target_ulong, as passed i
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
We now have the address size as part of the opcode, so we no longer need to test TARGET_LONG_BITS. We can use uint64_t for target_ulong, as passed into load/store helpers.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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fecccfcc |
| 16-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits, as we need one or two host registers to represent the guest address.
Create
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits, as we need one or two host registers to represent the guest address.
Create the new opcodes and update all users. Since we have not yet eliminated TARGET_LONG_BITS, only one of the two opcodes will ever be used, so we can get away with treating them the same in the backends.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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0bbf5015 |
| 08-Mar-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/tci: Use helper_{ld,st}*_mmu for user-only
We can now fold these two pieces of code.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@li
tcg/tci: Use helper_{ld,st}*_mmu for user-only
We can now fold these two pieces of code.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0 |
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0cadc1ed |
| 31-Oct-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Unify helper_{be,le}_{ld,st}*
With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of fu
tcg: Unify helper_{be,le}_{ld,st}*
With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of functions.
Hoist the qemu_{ld,st}_helpers arrays to tcg.c.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ae2b5d83 |
| 08-Feb-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-include-2023-02-06-v2' of https://repo.or.cz/qemu/armbru into staging
Header cleanup patches for 2023-02-06
# -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0A
Merge tag 'pull-include-2023-02-06-v2' of https://repo.or.cz/qemu/armbru into staging
Header cleanup patches for 2023-02-06
# -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmPjQRUSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTWHwQAI5D2HTRt3peFSPg/tFuYqSGtOobzM5x # xdZxjWCtGV+dZ4TsyQ7yJkQ2i6aPjs0LzmTnTIsmf+p1OJSthvp4fQUzfXQauiJy # OnNA76v7WjiXB8u8tcXtEkkHNmccp8n4KMjk33TfK/HQVx7lZ2EFurlCkvBr5wki # FuDVad6R43ChmvBWdCUOi6G1IklAihm8AN4lBJu3iC7U8bjW4FmLLMitcu5OyKgt # v9V4XFAe4eYUIPZ6uH5Lpr5m/qtrRXLe9KOdRUR2vDVL18Cf6Zl7mrUNtv7iV5TI # hBOA12ZP5XXf81FXl7e8y3Xi2KXvb/el0wQ7SvtE7XB3Pdbfa5WSGKOc3VxYLmBA # 4xUnEbzAogrrruovdk1bmh2LnVzCH66m72xaLCHBvjOU3M6V2B0eeaZ35FxNuFcB # toHPAjeuzWkDAscVYcYKuPwnkNOMNqHxEdihrgy6mYLr6nauIYr7Lqgs3SqGqpct # /HGy683+J+AqnHFTk1MTRftDxqk/Nku6ntAxLXndkpm3uDvu+iV5d3BfK3A9t7d1 # A2Y983DU6SiVwpMIv2eDL8sXYxuwIs56ZmPYIcSbqzpCXtdFqwWOTeFET/4vD+8t # V3YKJ27jmWQ9bxbLHGPPYSKheuCVBIGsqxouE/Pbj5nXRKm/TeGp+20a4dWdE08r # 2WTLAQbVQGD4 # =5TPW # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Feb 2023 06:28:37 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* tag 'pull-include-2023-02-06-v2' of https://repo.or.cz/qemu/armbru: Drop duplicate #include Don't include headers already included by qemu/osdep.h Fix non-first inclusions of qemu/osdep.h accel: Clean up includes block: Clean up includes riscv: Clean up includes target/hexagon: Clean up includes net: Clean up includes migration: Clean up includes qga: Clean up includes hw/tricore: Clean up includes hw/input: Clean up includes hw/cxl: Clean up includes crypto: Clean up includes bsd-user: Clean up includes scripts/clean-includes: Improve --git commit message scripts/clean-includes: Skip symbolic links scripts/clean-includes: Don't claim duplicate headers found when not scripts/clean-includes: Fully skip / ignore files
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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bfe7bf85 |
| 02-Feb-2023 |
Markus Armbruster <armbru@redhat.com> |
Don't include headers already included by qemu/osdep.h
This commit was created with scripts/clean-includes.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Christian Schoenebeck <qem
Don't include headers already included by qemu/osdep.h
This commit was created with scripts/clean-includes.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20230202133830.2152150-19-armbru@redhat.com>
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#
b5238812 |
| 04-Feb-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu into staging
tcg: Add support for TCGv_i128 in parameters and returns. tcg: Add support for TCGv_i128 in cmpxchg. tcg: Test CPUJumpCa
Merge tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu into staging
tcg: Add support for TCGv_i128 in parameters and returns. tcg: Add support for TCGv_i128 in cmpxchg. tcg: Test CPUJumpCache in tb_jmp_cache_clear_page tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target target/arm: Use tcg_gen_atomic_cmpxchg_i128 target/i386: Use tcg_gen_atomic_cmpxchg_i128 target/i386: Use tcg_gen_nonatomic_cmpxchg_i{32,64} target/s390x: Use tcg_gen_atomic_cmpxchg_i128 target/s390x: Use TCGv_i128 in passing and returning float128 target/s390x: Implement CC_OP_NZ in gen_op_calc_cc
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmPeiDYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+hFQf+K1MkEK1wtpjnqrYD # 4l36Uo3B7w8Yi6FxbCx9NP78dJNNTjTn0zqhtISRKSzI7TGUCGnmQs40iqYrRe5S # 9x6LJgTJplI2dsANvtsTaWB5gNzhowPt5tlit+J6Q0POwvvwcBZAOumY8AYt1YP+ # dMsjBLw6HFaqSCU5IERZrB4kBwl61VTkTAtHL2utSZpdsOYoc3y2hzbJ/w3kLK2u # YXnMvom+Gc1rvQTaSMgiPYFITyx/VtXDe+JQwNikpu7Na+RFjtu7cHmg/BtZFo6s # 15AsAS8JlENKAunpJiX41UR7SxB8MdyQL5LyjVNWo5F7+YgQuuO1gqYKt6qUwd+A # oH2uBA== # =xjMy # -----END PGP SIGNATURE----- # gpg: Signature made Sat 04 Feb 2023 16:30:46 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu: (40 commits) tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target target/i386: Inline cmpxchg16b target/i386: Inline cmpxchg8b target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b target/s390x: Implement CC_OP_NZ in gen_op_calc_cc target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG target/s390x: Use Int128 for passing float128 target/s390x: Use Int128 for returning float128 target/s390x: Copy wout_x1 to wout_x1_P target/s390x: Use Int128 for return from TRE target/s390x: Use Int128 for return from CKSM target/s390x: Use Int128 for return from CLST target/s390x: Use a single return for helper_divs64/u64 target/s390x: Use a single return for helper_divs32/u32 tests/tcg/s390x: Add cdsg.c tests/tcg/s390x: Add long-double.c tests/tcg/s390x: Add clst.c tests/tcg/s390x: Add div.c target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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e9709e17 |
| 20-Oct-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128
Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value le
tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128
Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length.
Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time now, but only fill in slots required for the call we're about to make.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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896c76e6 |
| 20-Oct-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/tci: Fix big-endian return register ordering
We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We
tcg/tci: Fix big-endian return register ordering
We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
aaa90fed |
| 06-Jan-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into staging
Fix race conditions in new user-only vma tracking. Add tcg backend paired register allocation. Cleanup tcg backend funct
Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into staging
Fix race conditions in new user-only vma tracking. Add tcg backend paired register allocation. Cleanup tcg backend function call abi.
# gpg: Signature made Fri 06 Jan 2023 03:12:17 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu: (47 commits) tests/tcg/multiarch: add vma-pthread.c accel/tcg: Handle false negative lookup in page_check_range accel/tcg: Use g_free_rcu for user-exec interval trees accel/tcg: Fix tb_invalidate_phys_page_unwind tcg: Add TCGHelperInfo argument to tcg_out_call tcg/aarch64: Merge tcg_out_callr into tcg_out_call tcg: Move ffi_cif pointer into TCGHelperInfo tcg: Factor init_ffi_layouts() out of tcg_context_init() tcg: Convert typecode_to_ffi from array to function tcg: Reorg function calls tcg: Use output_pref wrapper function tcg: Vary the allocation size for TCGOp tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*() accel/tcg/plugin: Use copy_op in append_{udata,mem}_cb accel/tcg/plugin: Avoid duplicate copy in copy_call accel/tcg/plugin: Don't search for the function pointer index tcg: Use TCG_CALL_ARG_EVEN for TCI special case tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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7789b16d |
| 10-Nov-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tci: MAX_OPC_PARAM_IARGS is no longer used
Unused since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <r
tci: MAX_OPC_PARAM_IARGS is no longer used
Unused since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1be5a765 |
| 19-Apr-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Add cpu0-id to query-sev-capabilities * whpx support for breakpoints and stepping * initial support for Hyper-V Synthetic D
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Add cpu0-id to query-sev-capabilities * whpx support for breakpoints and stepping * initial support for Hyper-V Synthetic Debugging * use monotonic clock for QemuCond and QemuSemaphore * Remove qemu-common.h include from most units and lots of other clenaups * do not include headers for all virtio devices in virtio-ccw.h
# -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmJXCQAUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNT6wf+NHDJUEdDiwaVGVTGXgHuiaycsymi # FpNPiw/+XxSGN5xF3fkUGgqaDrcwIYwVfnXlghKSz8kp1cP3cjxa5CzNMLGTp5je # N6BxFbD7yC6dhagGm3mj32jlsptv3M38OHqKc3t+RaUAotP5RF2VdCyfUBLG6vU0 # aMzvMfMtB5aG0D8Fr5EV63t1JMTceFU0YxsG73UCFs2Yx4Z0cGBbNxMbHweRhd1q # tPeVDS46MFPM3/2cGGHpeeqxkoCTU7A9j1VuNQI3k+Kg+6W5YVxiK/UP7bw77E/a # yAHsmIVTNro8ajMBch73weuHtGtdfFLvCKc6QX6aVjzK4dF1voQ01E7gPQ== # =rMle # -----END PGP SIGNATURE----- # gpg: Signature made Wed 13 Apr 2022 10:31:44 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (53 commits) target/i386: Remove unused XMMReg, YMMReg types and CPUState fields target/i386: do not access beyond the low 128 bits of SSE registers virtio-ccw: do not include headers for all virtio devices virtio-ccw: move device type declarations to .c files virtio-ccw: move vhost_ccw_scsi to a separate file s390x: follow qdev tree to detect SCSI device on a CCW bus hw: hyperv: Initial commit for Synthetic Debugging device hyperv: Add support to process syndbg commands hyperv: Add definitions for syndbg hyperv: SControl is optional to enable SynIc thread-posix: optimize qemu_sem_timedwait with zero timeout thread-posix: implement Semaphore with QemuCond and QemuMutex thread-posix: use monotonic clock for QemuCond and QemuSemaphore thread-posix: remove the posix semaphore support whpx: Added support for breakpoints and stepping build-sys: simplify AF_VSOCK check build-sys: drop ntddscsi.h check Remove qemu-common.h include from most units qga: remove explicit environ argument from exec/spawn Move fcntl_setfl() to oslib-posix ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.0.0 |
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0f9668e0 |
| 23-Mar-2022 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
Remove qemu-common.h include from most units
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo B
Remove qemu-common.h include from most units
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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50a75ff6 |
| 14-Feb-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220211' into staging
Fix safe_syscall_base for sparc64. Fix host signal handling for sparc64-linux. Speedups for jump cache and work
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220211' into staging
Fix safe_syscall_base for sparc64. Fix host signal handling for sparc64-linux. Speedups for jump cache and work list probing. Fix for exception replays. Raise guest SIGBUS for user-only misaligned accesses.
# gpg: Signature made Fri 11 Feb 2022 01:27:16 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20220211: (34 commits) tests/tcg/multiarch: Add sigbus.c tcg/sparc: Support unaligned access for user-only tcg/sparc: Add tcg_out_jmpl_const for better tail calls tcg/sparc: Use the constant pool for 64-bit constants tcg/sparc: Convert patch_reloc to return bool tcg/sparc: Improve code gen for shifted 32-bit constants tcg/sparc: Add scratch argument to tcg_out_movi_int tcg/sparc: Split out tcg_out_movi_imm32 tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64 tcg/mips: Support unaligned access for softmmu tcg/mips: Support unaligned access for user-only tcg/arm: Support raising sigbus for user-only tcg/arm: Reserve a register for guest_base tcg/arm: Support unaligned access for softmmu tcg/arm: Check alignment for ldrd and strd tcg/arm: Remove use_armv6_instructions tcg/arm: Remove use_armv5t_instructions tcg/arm: Drop support for armv4 and armv5 hosts tcg/loongarch64: Support raising sigbus for user-only tcg/tci: Support raising sigbus for user-only ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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