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Searched refs:TCG_COND_EQ (Results 1 – 25 of 70) sorted by relevance

123

/openbmc/qemu/target/hexagon/
H A Dgen_tcg.h334 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
391 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
566 gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ);
570 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
574 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
579 gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0])
583 gen_cond_return_subinsn(ctx, TCG_COND_EQ, ctx->new_pred_value[0])
700 gen_cond_call(ctx, PuV, TCG_COND_EQ, riV)
704 gen_cond_callr(ctx, TCG_COND_EQ, PuV, RsV)
761 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
[all …]
H A Dgen_tcg_hvx.h447 fGEN_TCG_VEC_CMP(TCG_COND_EQ, MO_32, 4)
449 fGEN_TCG_VEC_CMP(TCG_COND_EQ, MO_16, 2)
451 fGEN_TCG_VEC_CMP(TCG_COND_EQ, MO_8, 1)
506 fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_and)
508 fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_or)
510 fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_xor)
513 fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_and)
515 fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_or)
517 fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_xor)
520 fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_and)
[all …]
H A Dgenptr.c365 tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val, in gen_store_conditional4()
390 tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64, in gen_store_conditional8()
632 gen_cmpnd_cmp_jmp(ctx, pnum, cond, arg1, arg2, TCG_COND_EQ, pc_off); in gen_cmpnd_cmp_jmp_t()
647 gen_cmpnd_cmp_jmp(ctx, pnum, cond, arg1, tmp, TCG_COND_EQ, pc_off); in gen_cmpnd_cmpi_jmp_t()
869 tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2); in gen_endloop0()
942 tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2); in gen_endloop01()
980 gen_cond_jump(ctx, TCG_COND_EQ, pred, pc_off); in gen_cmp_jumpnv()
988 gen_cond_jump(ctx, TCG_COND_EQ, pred, pc_off); in gen_cmpi_jumpnv()
1019 tcg_gen_movcond_tl(TCG_COND_EQ, tmp, sh32, shift_amt, in gen_shl_sat()
1029 tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, tmp, satval); in gen_shl_sat()
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvm.c.inc191 tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
192 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
200 tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
201 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
233 tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
234 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
266 tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
267 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
275 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
280 tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
[all …]
H A Dtrans_rvzicond.c.inc35 gen_czero(dest, src1, src2, TCG_COND_EQ);
H A Dtrans_rvzicfiss.c.inc33 tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip);
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_branch.c.inc75 TRANS(beq, ALL, gen_rr_bc, TCG_COND_EQ)
81 TRANS(beqz, ALL, gen_rz_bc, TCG_COND_EQ)
83 TRANS(bceqz, 64, gen_cz_bc, TCG_COND_EQ)
H A Dtrans_arith.c.inc124 tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, INT64_MIN);
125 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, src2, -1);
126 tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src2, 0);
142 tcg_gen_movcond_tl(TCG_COND_EQ, ret, src2, zero, one, src2);
H A Dtrans_atomic.c.inc32 tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);
41 tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval);
/openbmc/qemu/target/avr/
H A Dtranslate.c282 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ in gen_ZNSf()
364 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ in trans_ADIW()
446 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); in trans_SBC()
476 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); in trans_SBCI()
511 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ in trans_SBIW()
535 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ in trans_AND()
675 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80); /* Vf = Rd == 0x80 */ in trans_INC()
697 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f); /* Vf = Rd == 0x7f */ in trans_DEC()
724 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ in trans_MUL()
754 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ in trans_MULS()
[all …]
/openbmc/qemu/target/mips/tcg/
H A Docteon_translate.c150 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); in trans_SEQNE()
173 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); in trans_SEQNEI()
H A Dtx79_translate.c282 return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); in trans_PCEQB()
294 return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); in trans_PCEQH()
306 return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32); in trans_PCEQW()
H A Dtranslate.c2229 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); in gen_st_cond()
2239 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); in gen_st_cond()
2718 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); in gen_cond_move()
2724 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); in gen_cond_move()
3031 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); in gen_r6_muldiv()
3032 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3034 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); in gen_r6_muldiv()
3047 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); in gen_r6_muldiv()
3048 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3050 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); in gen_r6_muldiv()
[all …]
H A Dmxu_translate.c1048 tcg_gen_brcondi_tl(TCG_COND_EQ, rounding, 0, l_done); in gen_mxu_d16mul()
1062 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_half_done); in gen_mxu_d16mul()
1068 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_done); in gen_mxu_d16mul()
1173 tcg_gen_brcondi_tl(TCG_COND_EQ, rounding, 0, l_done); in gen_mxu_d16mac()
1187 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_half_done); in gen_mxu_d16mac()
1193 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_done); in gen_mxu_d16mac()
3714 tcg_gen_brcondi_tl(TCG_COND_EQ, t4, 0, l_zero); in gen_mxu_s32extrv()
3946 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_c_hi); in gen_mxu_q16scop()
3968 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_done); in gen_mxu_q16scop()
4312 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_b_only); in gen_mxu_S32ALN()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-m-nocp.c140 tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel.label); in trans_VSCCLRM()
292 assert(cond == TCG_COND_EQ || cond == TCG_COND_NE); in gen_branch_fpInactive()
355 gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); in gen_M_fp_sysreg_write()
507 gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); in gen_M_fp_sysreg_read()
541 tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), in gen_M_fp_sysreg_read()
/openbmc/qemu/target/tricore/
H A Dtranslate.c315 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, in gen_cmpswap()
1015 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); in gen_madd32_q()
1016 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); in gen_madd32_q()
1044 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); in gen_m16add32_q()
1061 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); in gen_m16adds32_q()
1083 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); in gen_m16add64_q()
1109 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); in gen_m16adds64_q()
1150 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); in gen_madd64_q()
1151 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); in gen_madd64_q()
1777 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); in gen_m16sub32_q()
[all …]
/openbmc/qemu/target/sh4/
H A Dtranslate.c273 TCGCond cond_not_taken = jump_if_true ? TCG_COND_EQ : TCG_COND_NE; in gen_conditional_jump()
310 tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1); in gen_delayed_conditional_jump()
727 tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
777 tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, zero, REG(B7_4), t2); in _decode_opc()
955 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1173 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); in _decode_opc()
1280 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1289 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1357 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1531 tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_value); in _decode_opc()
[all …]
/openbmc/qemu/include/tcg/
H A Dtcg-cond.h42 TCG_COND_EQ = 8 | 0 | 0 | 0, enumerator
/openbmc/qemu/target/rx/
H A Dtranslate.c255 dc->cond = TCG_COND_EQ; in psw_cond()
267 dc->cond = TCG_COND_EQ; in psw_cond()
274 dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; in psw_cond()
296 dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; in psw_cond()
740 stcond(TCG_COND_EQ, a->rd, a->imm); in trans_STZ()
950 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); in rx_neg()
952 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); in rx_neg()
1291 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); in trans_SHLL_irr()
1292 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); in trans_SHLL_irr()
1314 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); in trans_SHLL_rr()
[all …]
/openbmc/qemu/target/ppc/
H A Dtranslate.c1759 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); in gen_op_arith_divw()
1760 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divw()
1762 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_divw()
1769 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); in gen_op_arith_divw()
1801 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_divd()
1802 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divd()
1804 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_divd()
1810 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); in gen_op_arith_divd()
1840 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); in gen_op_arith_modw()
1841 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modw()
[all …]
/openbmc/qemu/target/alpha/
H A Dtranslate.c426 tcg_gen_setcond_i64(TCG_COND_EQ, ctx->ir[ra], val, cpu_lock_value); in gen_store_conditional()
505 case TCG_COND_EQ: in gen_fold_mzero()
508 *pcond = *pcond == TCG_COND_EQ ? TCG_COND_TSTEQ : TCG_COND_TSTNE; in gen_fold_mzero()
516 tcg_gen_movcond_i64(TCG_COND_EQ, tmp, in gen_fold_mzero()
1561 tcg_gen_setcond_i64(TCG_COND_EQ, vc, va, vb); in translate_one()
1689 tcg_gen_movcond_i64(TCG_COND_EQ, vc, va, load_zero(ctx), in translate_one()
2246 gen_fcmov(ctx, TCG_COND_EQ, ra, rb, rc); in translate_one()
2791 ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21); in translate_one()
2823 ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21); in translate_one()
/openbmc/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc1153 tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1156 tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
1177 TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
1178 TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
1179 TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
1180 TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1203 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
1204 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
1271 tcg_gen_negsetcond_i64(TCG_COND_EQ, t1, t1, tcg_constant_i64(0));
1298 tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0));
[all …]
H A Dvsx-impl.c.inc1004 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t, b,
1013 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t, b,
1023 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t, b,
1030 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t, b,
1038 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t, b,
1047 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t, b,
1769 tcg_gen_setcond_i64(TCG_COND_EQ, all_false, all_false, zero);
1771 tcg_gen_setcond_i64(TCG_COND_EQ, all_true, all_true, mask);
1967 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
1968 tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
[all …]
/openbmc/qemu/target/openrisc/
H A Dtranslate.c271 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); in gen_div()
285 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); in gen_divu()
624 do_bf(dc, a, TCG_COND_EQ); in trans_l_bnf()
717 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); in trans_l_swa()
939 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, in trans_l_sfeq()
1009 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); in trans_l_sfeqi()
/openbmc/qemu/target/xtensa/
H A Dtranslate.c409 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); in gen_check_loop_end()
2216 tcg_gen_setcond_i32(TCG_COND_EQ, res, prev, cpu_exclusive_val); in translate_s32ex()
2217 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val, in translate_s32ex()
2771 .par = (const uint32_t[]){TCG_COND_EQ},
2785 .par = (const uint32_t[]){TCG_COND_EQ},
2792 .par = (const uint32_t[]){TCG_COND_EQ},
2813 .par = (const uint32_t[]){TCG_COND_EQ},
2820 .par = (const uint32_t[]){TCG_COND_EQ},
2827 .par = (const uint32_t[]){TCG_COND_EQ},
2832 .par = (const uint32_t[]){TCG_COND_EQ},
[all …]

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