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Searched refs:SW2 (Results 1 – 25 of 54) sorted by relevance

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/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME17 SW2 x100 0000
24 SW2 0100 0000
31 SW2 1100 0000
73 SW2 x110 1111
77 SW2 0110 1111
81 SW2 0110 1111
85 SW2 1110 1111
89 SW2 1110 1111
/openbmc/u-boot/doc/
H A DREADME.mpc85xxcds88 SW2[2] on the carrier card before resetting the board in order to set the
101 The first two bits of SW2 control how flash is used on the board:
105 SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
114 connected.. By convention, the user-specific bits of SW2 are used to
119 SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
133 SW2=0x1111yy x=Flash bank, yy=PCI slot
158 SW2=01000111
172 SW2=10011111
H A DREADME.b4860qds123 SW2 ON ON ON ON ON ON OFF OFF
135 SW2 [1.1] = 1
139 SW2 [1.1] = 0
148 SW2 ON OFF ON OFF ON ON OFF OFF
160 SW2 [1.1] = 1
164 SW2 [1.1] = 0
/openbmc/u-boot/board/sbc8548/
H A DREADME36 card. [The above discussion assumes that the SW2[1-4] has not been changed
194 alternate setting, you also need to switch SW2.8 to ON.
207 SW2.1 CFG_SYS_PLL0 1 0*
208 SW2.2 CFG_SYS_PLL1 1* 0
209 SW2.3 CFG_SYS_PLL2 1* 0
210 SW2.4 CFG_SYS_PLL3 1 0*
211 SW2.5 CFG_CORE_PLL0 1* 0
212 SW2.6 CFG_CORE_PLL1 1 0*
213 SW2.7 CFG_CORE_PLL2 1* 0
214 SW2.8 CFG_ROM_LOC1 1 0*
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7792-blanche.dts117 label = "SW2-1";
124 label = "SW2-2";
131 label = "SW2-3";
138 label = "SW2-4";
H A Dr8a7793-gose.dts70 label = "SW2-1";
77 label = "SW2-2";
84 label = "SW2-3";
91 label = "SW2-4";
H A Dr8a7791-koelsch.dts84 label = "SW2-1";
91 label = "SW2-2";
98 label = "SW2-3";
105 label = "SW2-4";
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dsh73a0-kzm9g.dts113 label = "SW2-R";
119 label = "SW2-L";
125 label = "SW2-P";
131 label = "SW2-U";
137 label = "SW2-D";
H A Dr8a7792-blanche.dts120 label = "SW2-1";
127 label = "SW2-2";
134 label = "SW2-3";
141 label = "SW2-4";
H A Dr8a7794-alt.dts106 label = "SW2-1";
113 label = "SW2-2";
120 label = "SW2-3";
127 label = "SW2-4";
H A Dr8a7793-gose.dts76 label = "SW2-1";
83 label = "SW2-2";
90 label = "SW2-3";
97 label = "SW2-4";
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME287 SW2: 10111011
292 SW2: 00111011
297 SW2: 10111011
302 SW2: 00111011
309 SW2: 10111001
314 SW2: 00111001
319 SW2: 10111001
324 SW2: 00111001
/openbmc/u-boot/board/freescale/mx35pdk/
H A DREADME14 switch the boot device with the switches SW1-SW2 on the Personality board,
77 (SW1-SW2) and on the DEBUG board (SW4-SW10).
105 SW2 all off
/openbmc/u-boot/board/freescale/mpc8536ds/
H A DREADME36 SW2[5-8] = 1011
70 SW2[5-8] = 0111
123 SW2[5-8] = 0110
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
90 SW2 {
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME142 SW2[1:8] = '10111111'
154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
184 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
193 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
/openbmc/linux/drivers/regulator/
H A Dpcap-regulator.c132 VREG_INFO(SW2, PCAP_REG_SWCTRL, 6, 7, NA, NA),
228 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
H A Dpfuze100-regulator.c373 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
391 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
409 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
424 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME18 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
19 SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
237 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
248 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
/openbmc/u-boot/board/liebherr/display5/
H A Ddisplay5.c51 #define SW2 IMX_GPIO_NR(2, 6) macro
63 SW0, SW1, SW2, SW3
/openbmc/u-boot/include/power/
H A Dmc34vr500_pmic.h166 SW2, enumerator
/openbmc/linux/Documentation/networking/
H A Darcnet-hardware.rst803 < | SW1 | | SW2 | |
831 SW2 1-6: Reserved for Future Use
1051 | | | SW2 |
1064 SW2: DIP-Switches for Memory Base and I/O Base addresses
1087 The I/O base address is coded with DIP-Switches 6,7 and 8 of SW2:
1104 DIP Switches 1-5 of SW2 encode the RAM and ROM Address Range:
1377 The eight switches in SW2 are used to set the node ID. Each node attached
1575 SW2 1-8: Node ID Select (ID0-ID7)
1588 The eight switches in SW2 are used to set the node ID. Each node attached
1833 | |SW2| |
[all …]
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME171 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
190 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
201 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
212 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
/openbmc/linux/Documentation/hid/
H A Dhid-alps.rst114 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
164 Byte1 1 1 1 0 1 SW3 SW2 SW1

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