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Searched refs:SW1 (Results 1 – 25 of 62) sorted by relevance

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/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044c2-smarc.dts11 * DIP-Switch SW1 setting on SoM
13 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
16 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
17 * Please change below macros according to SW1 setting
40 * - Set DIP-Switch SW1-4 to Off position.
H A Dr9a07g043u11-smarc.dts11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
22 * - Set DIP-Switch SW1-3 to On position.
H A Drzg2l-smarc-som.dtsi12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
17 * SW1[2] should be at position 3/ON.
240 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
243 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
244 * SW1[2] should be at position 3/ON to enable uSD card CN3
H A Drzg2lc-smarc-som.dtsi169 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
172 * SW1[2] should be at OFF position to enable 64 GB eMMC
173 * SW1[2] should be at position ON to enable uSD card CN3
/openbmc/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f01-smarc.dts11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME16 SW1 0011 0001
23 SW1 0010 0000
30 SW1 0010 0000
72 SW1 0001 0010
76 SW1 0011 0001
80 SW1 0010 0000
84 SW1 0010 0000
88 SW1 0010 0100
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7779-marzen.dts81 label = "SW1-1";
88 label = "SW1-2";
104 label = "SW1-3";
110 label = "SW1-4";
/openbmc/u-boot/board/kobol/helios4/
H A DREADME23 Before powering up the board, boot selection should be done via the SW1 dip
37 Set the SW1 DIP switches to UART boot (see above).
/openbmc/u-boot/board/freescale/p2041rdb/
H A DREADME37 SW1[1-5] = 10110
60 SW1[1-5] = 01100
85 SW1[1-5] = 10100
/openbmc/u-boot/doc/
H A DREADME.pblimage41 Change SW1[1:5] = off off on off on.
49 Change SW1[1:5] = off off on on off.
58 Change SW1[1:5] = off on off off on
H A DREADME.b4860qds122 SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
134 SW1 [1.1] = 0
138 SW1 [1.1] = 1
147 SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
159 SW1 [1.1] = 0
163 SW1 [1.1] = 1
H A DREADME.mpc85xxcds132 SW1=01101100
157 SW1=10001111
171 SW1=11111101
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME286 SW1: 00010011
291 SW1: 10001000
296 SW1: 00100010
301 SW1: 00100000
308 SW1: 00010011
313 SW1: 10001000
318 SW1: 00100010
323 SW1: 00100000
/openbmc/linux/Documentation/hid/
H A Dhid-alps.rst114 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
148 SW1-SW6:
164 Byte1 1 1 1 0 1 SW3 SW2 SW1
173 SW1-SW3:
/openbmc/u-boot/board/solidrun/clearfog/
H A DREADME23 Before powering up the board, boot selection should be done via the SW1 dip
42 Set the SW1 DIP switches to UART boot (see above).
/openbmc/u-boot/board/freescale/mx35pdk/
H A DREADME14 switch the boot device with the switches SW1-SW2 on the Personality board,
77 (SW1-SW2) and on the DEBUG board (SW4-SW10).
106 SW1 all off
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB64 SW1[1:8]= 10101010
91 SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
153 set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
157 set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
84 SW1 {
/openbmc/linux/Documentation/networking/
H A Darcnet-hardware.rst803 < | SW1 | | SW2 | |
829 SW1 1-6: I/O Base Address Select
889 The first six switches in switch group SW1 are used to select one
932 Switches seven through ten of switch group SW1 are used to select the
1063 SW1: DIP-Switches for Station Address
1085 The station address is binary-coded with SW1.
1341 | | 90C65 || SW1 | ____|
1419 The last three switches in switch block SW1 are used to select one
1442 Switches 1-5 of switch block SW1 select the Memory Base address.
1554 < | PROM | | SW1 | A | 2 | ID3
[all …]
/openbmc/u-boot/board/boundary/nitrogen6x/
H A DREADME.mx6qsabrelite43 the board). Make sure SW1 switch is at position "00", so that it can boot
106 3. Make sure SW1 switch is at position "01", so that it can boot from USB OTG.
118 6. Ensure SW1 is returned to "00" to boot from the fuses once done.
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME141 SW1[1:8] = '00010011'
154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
184 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
193 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
/openbmc/linux/drivers/regulator/
H A Dpcap-regulator.c131 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
228 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
237 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
248 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
/openbmc/u-boot/board/liebherr/display5/
H A Ddisplay5.c50 #define SW1 IMX_GPIO_NR(2, 5) macro
63 SW0, SW1, SW2, SW3
/openbmc/u-boot/include/power/
H A Dmc34vr500_pmic.h165 SW1 = 0, enumerator

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