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Searched refs:RVH (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvh.c.inc67 REQUIRE_EXT(ctx, RVH);
73 REQUIRE_EXT(ctx, RVH);
79 REQUIRE_EXT(ctx, RVH);
85 REQUIRE_EXT(ctx, RVH);
91 REQUIRE_EXT(ctx, RVH);
97 REQUIRE_EXT(ctx, RVH);
103 REQUIRE_EXT(ctx, RVH);
109 REQUIRE_EXT(ctx, RVH);
116 REQUIRE_EXT(ctx, RVH);
123 REQUIRE_EXT(ctx, RVH);
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H A Dtrans_svinval.c.inc58 REQUIRE_EXT(ctx, RVH);
71 REQUIRE_EXT(ctx, RVH);
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c262 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { in riscv_cpu_validate_misa_priv()
446 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions()
452 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { in riscv_cpu_validate_set_extensions()
1006 if (riscv_has_ext(env, RVH)) { in riscv_tcg_cpu_realize()
1049 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { in cpu_set_misa_ext_cfg()
1088 MISA_CFG(RVH, true),
/openbmc/qemu/target/riscv/
H A Dcsr.c346 if (riscv_has_ext(env, RVH)) { in hmode()
881 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfg()
883 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfg()
907 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfgh()
909 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfgh()
934 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfg()
936 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfg()
958 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfgh()
960 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfgh()
992 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mhpmevent()
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H A Dcpu_helper.c629 g_assert(riscv_has_ext(env, RVH)); in riscv_cpu_swap_hypervisor_regs()
682 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_get_geilen()
691 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_geilen()
801 if (riscv_has_ext(env, RVH)) { in riscv_cpu_set_mode()
1916 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
1970 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
H A Dop_helper.c295 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret()
356 if (riscv_has_ext(env, RVH) && prev_virt) { in helper_mret()
H A Dcpu.c45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
547 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init()
757 if (riscv_has_ext(env, RVH)) { in riscv_cpu_dump_state()
952 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold()
995 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold()
1289 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_irq()
1408 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
H A Dmachine.c77 return riscv_has_ext(env, RVH); in hyper_needed()
H A Dcpu.h73 #define RVH RV('H') macro
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H),