Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging

RISC-V PR for 9.2

* Fix an access to VXSAT
* Expose RV32 cpu to RV64 QEMU
* Don't clear PLIC pending bi

Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging

RISC-V PR for 9.2

* Fix an access to VXSAT
* Expose RV32 cpu to RV64 QEMU
* Don't clear PLIC pending bits on IRQ lowering
* Make PLIC zeroth priority register read-only
* Set vtype.vill on CPU reset
* Check and update APLIC pending when write sourcecfg
* Avoid dropping charecters with HTIF
* Apply FIFO backpressure to guests using SiFive UART
* Support for control flow integrity extensions
* Support for the IOMMU with the virt machine
* set 'aia_mode' to default in error path
* clarify how 'riscv-aia' default works

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmci/tQACgkQr3yVEwxT
# gBNPAQ//dZKjjJm4Sh+UFdUslivBJYtL1rl2UUG2UqiNn/UoYh/vcHoSArljHTjt
# 8riEStnaQqXziOpMIJjIMLJ4KoiIk2SMvjNfFtcmPiPZEDEpjsTxfUxBFsBee+fI
# 4KNQKKFeljq4pa+VzVvXEqzCNJIzCThFXTZhZmer00M91HPA8ZQIHpv2JL1sWlgZ
# /HW24XEDFLGc/JsR55fxpPftlAqP+BfOrqMmbWy7x2Y+G8WI05hM2zTP/W8pnIz3
# z0GCRYSBlADtrp+3RqzTwQfK5pXoFc0iDktWVYlhoXaeEmOwo8IYxTjrvBGhnBq+
# ySX1DzTa23QmOIxSYYvCRuOxyOK9ziNn+EQ9FiFBt1h1o251CYMil1bwmYXMCMNJ
# rZwF1HfUx0g2GQW1ZOqh1eeyLO29JiOdV3hxlDO7X4bbISNgU6il5MXmnvf0/XVW
# Af3YhALeeDbHgHL1iVfjafzaviQc9+YrEX13eX6N2AjcgE5a3F7XNmGfFpFJ+mfQ
# CPgiwVBXat6UpBUGAt14UM+6wzp+crSgQR5IEGth+mKMKdkWoykvo7A2oHdu39zn
# 2cdzsshg2qcLLUPTFy06OOTXX382kCWXuykhHOjZ4uu2SJJ7R0W3PlYV8HSde2Vu
# Rj+89ZlUSICJNXXweQB39r87hNbtRuDIO22V0B9XrApQbJj6/yE=
# =rPaa
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 31 Oct 2024 03:51:48 GMT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu: (50 commits)
target/riscv: Fix vcompress with rvv_ta_all_1s
target/riscv/kvm: clarify how 'riscv-aia' default works
target/riscv/kvm: set 'aia_mode' to default in error path
docs/specs: add riscv-iommu
qtest/riscv-iommu-test: add init queues test
hw/riscv/riscv-iommu: add DBG support
hw/riscv/riscv-iommu: add ATS support
hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
test/qtest: add riscv-iommu-pci tests
hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
hw/riscv: add riscv-iommu-pci reference device
pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
hw/riscv: add RISC-V IOMMU base emulation
hw/riscv: add riscv-iommu-bits.h
exec/memtxattr: add process identifier to the transaction attributes
target/riscv: Expose zicfiss extension as a cpu property
disas/riscv: enable disassembly for compressed sspush/sspopchk
disas/riscv: enable disassembly for zicfiss instructions
target/riscv: compressed encodings for sspush and sspopchk
target/riscv: implement zicfiss instructions
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/riscv: update `decode_save_opc` to store extra word2

Extra word 2 is stored during tcg compile and `decode_save_opc` needs
additional argument in order to pass the value. This will be used du

target/riscv: update `decode_save_opc` to store extra word2

Extra word 2 is stored during tcg compile and `decode_save_opc` needs
additional argument in order to pass the value. This will be used during
unwind to get extra information about instruction like how to massage
exceptions. Updated all callsites as well.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-16-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge tag 'pull-tcg-20231004' of https://gitlab.com/rth7680/qemu into staging

accel: Introduce AccelClass::cpu_common_[un]realize
accel: Target agnostic code movement
accel/tcg: Cleanups to use CPUS

Merge tag 'pull-tcg-20231004' of https://gitlab.com/rth7680/qemu into staging

accel: Introduce AccelClass::cpu_common_[un]realize
accel: Target agnostic code movement
accel/tcg: Cleanups to use CPUState instead of CPUArchState
accel/tcg: Move CPUNegativeOffsetState into CPUState
tcg: Split out tcg init functions to tcg/startup.h
linux-user/hppa: Fix struct target_sigcontext layout
build: Remove --enable-gprof

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmUdsL4dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/iYggAvDJEyMCAXSSH97BA
# wZT/2D/MFIhOMk6xrQRnrXfrG70N0iVKz44jl9j7k1D+9BOHcso//DDJH3c96k9A
# MgDb6W2bsWvC15/Qw6BALf5bb/II0MJuCcQvj3CNX5lNkXAWhwIOBhsZx7V9ST1+
# rihN4nowpRWdV5GeCjDGaJW455Y1gc96hICYHy6Eqw1cUgUFt9vm5aYU3FHlat29
# sYRaVYKUL2hRUPPNcPiPq0AaJ8wN6/s8gT+V1UvTzkhHqskoM4ZU89RchuXVoq1h
# SvhKElyULMRzM7thWtpW8qYJPj4mxZsKArESvHjsunGD6KEz3Fh1sy6EKRcdmpG/
# II1vkg==
# =k2Io
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 04 Oct 2023 14:36:46 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20231004' of https://gitlab.com/rth7680/qemu: (47 commits)
tcg/loongarch64: Fix buid error
tests/avocado: Re-enable MIPS Malta tests (GitLab issue #1884 fixed)
build: Remove --enable-gprof
linux-user/hppa: Fix struct target_sigcontext layout
tcg: Split out tcg init functions to tcg/startup.h
tcg: Remove argument to tcg_prologue_init
accel/tcg: Make cpu-exec-common.c a target agnostic unit
accel/tcg: Make icount.o a target agnostic unit
accel/tcg: Make monitor.c a target-agnostic unit
accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h'
exec: Rename target specific page-vary.c -> page-vary-target.c
exec: Rename cpu.c -> cpu-target.c
accel: Rename accel-common.c -> accel-target.c
accel: Make accel-blocker.o target agnostic
accel/tcg: Restrict dump_exec_info() declaration
exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h'
exec: Make EXCP_FOO definitions target agnostic
accel/tcg: move ld/st helpers to ldst_common.c.inc
accel/tcg: Unify user and softmmu do_[st|ld]*_mmu()
accel/tcg: Remove env_tlb()
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tcg: Rename cpu_env to tcg_env

Allow the name 'cpu_env' to be used for something else.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@li

tcg: Rename cpu_env to tcg_env

Allow the name 'cpu_env' to be used for something else.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging

First RISC-V PR for 8.1

* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse

Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging

First RISC-V PR for 8.1

* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmRUU48ACgkQr3yVEwxT
# gBP6gxAAyhmz7dKOPIb8RtUR4IT+SQhKYZEoSewy4xlXazZvh03K0jiYlEKcPLG+
# al50WlwL8ISsYwwpnatQr0deoeXnz9+qrSv7ikrzyqZScS8JTcJb/pdQnOz6WK3s
# 3FCBnBsYyjpdV6a2uCC9qck7xKTUpa9Gjx06DOuIoLfS8aFvf7Z3EbvsEyyDTEIi
# kwB0j5kdQkJLyx993F3atupjZSxvFmLJdtU4+IVYiOeBEVRD1iZth9KB9L9zjA49
# s+qTHg+afEr3GDlR02So9hYxyHqTHgRI8gkPaVN+ReEErC0nJNcx7/7tEhsLsswY
# fUAmsMnXaYOnEWFTJ+D/161rKx6QXwkX7bYCmPJFLGmzw5LWdK7JHEoXylRffuay
# Zh2e2tNky7QXPqp9fU0DBb9Xpbr0wHorLqFT8X8cuaI6r92weunZHx9zulhm11WA
# m0Q1UZaqAsnIL98UZocZr6C1hzR/OJ2QfjHDsKuPJEi8ylb7yRi4adcPn8YGBYX+
# 4YDNSvanegQq0g7gO3kSV/Cqweqm2xoDQyiRdyHWLQK2yJiZJTy07unzi+H7Dubf
# JR9bkdHTKz6Ywrf8hqw4yRqk5sPyamxHdXbhTDohUaPPQcfwQUraRdxIv1AQ94A1
# j+msUYpIZHjb5q2DtNHI1hQMdkVGRLMlfA8kpB+EcY1sXiqSky8=
# =fVG8
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 05 May 2023 01:53:35 AM BST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu: (89 commits)
target/riscv: add Ventana's Veyron V1 CPU
riscv: Make sure an exception is raised if a pte is malformed
target/riscv: Fix Guest Physical Address Translation
target/riscv: Restore the predicate() NULL check behavior
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
target/riscv: add query-cpy-definitions support
target/riscv: add CPU QOM header
hw/intc/riscv_aplic: Zero init APLIC internal state
target/riscv: Reorg sum check in get_physical_address
target/riscv: Reorg access check in get_physical_address
target/riscv: Merge checks for reserved pte flags
target/riscv: Don't modify SUM with is_debug
target/riscv: Suppress pte update with is_debug
target/riscv: Move leaf pte processing out of level loop
target/riscv: Hoist pbmte and hade out of the level loop
target/riscv: Hoist second stage mode change to callers
target/riscv: Check SUM in the correct register
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
target/riscv: Move hstatus.spvp check to check_access_hlsv
target/riscv: Introduce mmuidx_2stage
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/riscv: Handle HLV, HSV via helpers

Implement these instructions via helpers, in expectation
of determining the mmu_idx to use at runtime. This allows
the permission check to also be moved ou

target/riscv: Handle HLV, HSV via helpers

Implement these instructions via helpers, in expectation
of determining the mmu_idx to use at runtime. This allows
the permission check to also be moved out of line, which
allows HLSX to be removed from TB_FLAGS.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

target/riscv: Reduce overhead of MSTATUS_SUM change

Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
ove

target/riscv: Reduce overhead of MSTATUS_SUM change

Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.

This patch creates a separate MMU index for S+SUM, so that it's not
necessary to flush tlb anymore when SUM changes. This is similar to how
ARM handles Privileged Access Never (PAN).

Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many
other syscalls benefit a lot from this too.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-3-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

target/riscv: Set opcode to env->bins for illegal/virtual instruction fault

decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_rai

target/riscv: Set opcode to env->bins for illegal/virtual instruction fault

decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge tag 'pull-riscv-to-apply-20230207' of https://github.com/alistair23/qemu into staging

Third RISC-V PR for QEMU 8.0

* Update disas for xnor/orn/andn and slli.uw
* Update opentitan IRQs
* Fix r

Merge tag 'pull-riscv-to-apply-20230207' of https://github.com/alistair23/qemu into staging

Third RISC-V PR for QEMU 8.0

* Update disas for xnor/orn/andn and slli.uw
* Update opentitan IRQs
* Fix rom code when Zicsr is disabled
* Update VS timer whenever htimedelta changes
* A collection of fixes for virtulisation
* Set tval for triggered watchpoints
* Cleanups for board and FDT creation
* Add support for the T-Head vendor extensions
* A fix for virtual instr exception
* Fix ctzw behavior
* Fix SBI getchar handler for KVM

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmPh+QQACgkQIeENKd+X
# cFSdHwf9HQkO8/zTnWUFCbLVQAV3RB32i6E26uNC4+fQBpcqRWAel2PMYGi6x0H/
# fU43B5YpS7Ddfcc1ql6pJlisqsjkIsQBYjOeUfiMozLIR0dvX14jgUMxc0A8e8sZ
# uv3iRXjkVz/7bEWIdflPcaXgXh74HcQCPgMDsteluZYaz4yRGP6SvI9UJHqe4tjI
# HbiYmP1pcWFGDsAlKx7KbHfH/v9CE03odN3MLzwdsGYekUaFkdLlj7hmyamnqbAh
# OR1y29i2od/8uJMeIu5R8rnGdWoWetCZWP0z2xv3rrZuUzMJ6VXHcdWsY9ycomJs
# rYA0NB/ezmnKX+QAf+8TzW2nybG+5Q==
# =XLpK
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Feb 2023 07:08:52 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20230207' of https://github.com/alistair23/qemu: (32 commits)
hw/riscv: virt: Simplify virt_{get,set}_aclint()
target/riscv: fix SBI getchar handler for KVM
target/riscv: fix ctzw behavior
target/riscv: fix for virtual instr exception
target/riscv: add a MAINTAINERS entry for XThead* extension support
RISC-V: Adding XTheadFmv ISA extension
RISC-V: Add initial support for T-Head C906
RISC-V: Set minimum priv version for Zfh to 1.11
RISC-V: Adding T-Head FMemIdx extension
RISC-V: Adding T-Head MemIdx extension
RISC-V: Adding T-Head MemPair extension
RISC-V: Adding T-Head multiply-accumulate instructions
RISC-V: Adding XTheadCondMov ISA extension
RISC-V: Adding XTheadBs ISA extension
RISC-V: Adding XTheadBb ISA extension
RISC-V: Adding XTheadBa ISA extension
RISC-V: Adding XTheadSync ISA extension
RISC-V: Adding XTheadCmo ISA extension
hw/riscv: change riscv_compute_fdt_addr() semantics
hw/riscv: split fdt address calculation from fdt load
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/riscv: Ensure opcode is saved for all relevant instructions

We should call decode_save_opc() for all relevant instructions which
can potentially generate a virtual instruction fault or a gues

target/riscv: Ensure opcode is saved for all relevant instructions

We should call decode_save_opc() for all relevant instructions which
can potentially generate a virtual instruction fault or a guest page
fault because generating transformed instruction upon guest page fault
expects opcode to be available. Without this, hypervisor will see
transformed instruction as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.

Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge tag 'pull-riscv-to-apply-20220703-1' of github.com:alistair23/qemu into staging

Fifth RISC-V PR for QEMU 7.1

* Fix register zero guarding for auipc and lui
* Ensure bins (mtval) is set correc

Merge tag 'pull-riscv-to-apply-20220703-1' of github.com:alistair23/qemu into staging

Fifth RISC-V PR for QEMU 7.1

* Fix register zero guarding for auipc and lui
* Ensure bins (mtval) is set correctly
* Minimize the calls to decode_save_opc
* Guard against PMP ranges with a negative size
* Implement mcountinhibit CSR
* Add support for hpmcounters/hpmevents
* Improve PMU implenentation
* Support mcycle/minstret write operation
* Fixup MSECCFG minimum priv check
* Ibex (OpenTitan) fixup priv version
* Fix bug resulting in always using latest priv spec
* Reduce FDT address alignment constraints
* Set minumum priv spec version for mcountinhibit
* AIA update to v0.3 of the spec

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmLA3r8ACgkQIeENKd+X
# cFQdFQf6A63mocJxSc0vqMTBNULwgcUKbRbnkazbFS4vtbo/YXioCGaHA8c8trKj
# HbZfJv64phOThj7Y8ifLozENjnHX7dHbspPOcWIK9yalvKLA4EB4+OI7LisoL1vg
# H4E+9nXSzskaCmJgwSM6WlS0Vf89VxL0CoBb3XqJocSaajstg1XpqrR9anTZlUhl
# N712cLze+bOxBHTdjtC5Kxuxj+zmNvcMmuhldIJRdPCW8P5v2yccNVc6+hrE3WUX
# 9jHGMthS4qC5oVhok14/tPoyL0QTZpU2DXrJPFGUigOvUHoMBfQ3Qhulx3/rGLZv
# 4SdTD9ASrNWJfa+eyHAPNw//5NxTYA==
# =N7VN
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 03 Jul 2022 05:41:43 AM +0530
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220703-1' of github.com:alistair23/qemu:
target/riscv: Update default priority table for local interrupts
target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
target/riscv: Set minumum priv spec version for mcountinhibit
hw/riscv: boot: Reduce FDT address alignment constraints
target/riscv: Don't force update priv spec version to latest
target/riscv: Ibex: Support priv version 1.11
target/riscv: Fixup MSECCFG minimum priv check
target/riscv: Support mcycle/minstret write operation
target/riscv: Add support for hpmcounters/hpmevents
target/riscv: Implement mcountinhibit CSR
target/riscv: pmu: Make number of counters configurable
target/riscv: pmu: Rename the counters extension to pmu
target/riscv: Implement PMU CSR predicate function for S-mode
target/riscv: Fix PMU CSR predicate function
target/riscv/pmp: guard against PMP ranges with a negative size
target/riscv: Minimize the calls to decode_save_opc
target/riscv: Remove generate_exception_mtval
target/riscv: Set env->bins in gen_exception_illegal
target/riscv: Remove condition guarding register zero for auipc and lui

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/riscv: Minimize the calls to decode_save_opc

The set of instructions that require decode_save_opc for
unwinding is really fairly small -- only insns that can
raise ILLEGAL_INSN at runtime. T

target/riscv: Minimize the calls to decode_save_opc

The set of instructions that require decode_save_opc for
unwinding is really fairly small -- only insns that can
raise ILLEGAL_INSN at runtime. This includes CSR, anything
that uses a *new* fp rounding mode, and many privileged insns.

Since unwind info is stored as the difference from the
previous insn, storing a 0 for most insns minimizes the
size of the unwind info.

Booting a debian kernel image to the missing rootfs panic yields

- gen code size 22226819/1026886656
+ gen code size 21601907/1026886656

on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.0

- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- Si

Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.0

- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions

# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

exec/memop: Adding signedness to quad definitions

Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit

exec/memop: Adding signedness to quad definitions

Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging

First RISC-V PR for QEMU 6.2

- Add a config for Shakti UART
- Fixup virt flash node
- Don't overr

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging

First RISC-V PR for QEMU 6.2

- Add a config for Shakti UART
- Fixup virt flash node
- Don't override users supplied ISA version
- Fixup some CSR accesses
- Use g_strjoinv() for virt machine PLIC string config
- Fix an overflow in the SiFive CLINT
- Add 64-bit register access helpers
- Replace tcg_const_* with direct constant usage

# gpg: Signature made Wed 01 Sep 2021 03:08:48 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210901-2: (33 commits)
target/riscv: Use {get,dest}_gpr for RVV
target/riscv: Tidy trans_rvh.c.inc
target/riscv: Use {get,dest}_gpr for RVD
target/riscv: Use {get,dest}_gpr for RVF
target/riscv: Use gen_shift_imm_fn for slli_uw
target/riscv: Use {get,dest}_gpr for RVA
target/riscv: Reorg csr instructions
target/riscv: Fix hgeie, hgeip
target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
target/riscv: Use {get, dest}_gpr for integer load/store
target/riscv: Use get_gpr in branches
target/riscv: Use extracts for sraiw and srliw
target/riscv: Use DisasExtend in shift operations
target/riscv: Add DisasExtend to gen_unary
target/riscv: Move gen_* helpers for RVB
target/riscv: Move gen_* helpers for RVM
target/riscv: Use gen_arith for mulh and mulhu
target/riscv: Remove gen_arith_div*
target/riscv: Add DisasExtend to gen_arith*
target/riscv: Introduce DisasExtend and new helpers
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/riscv: Tidy trans_rvh.c.inc

Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use dest_gpr, get_gpr in the new subroutines.

Reviewed-by: Philippe Mathieu-Daudé

target/riscv: Tidy trans_rvh.c.inc

Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use dest_gpr, get_gpr in the new subroutines.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-24-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr

We will require the context to handle RV64 word operations.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng

target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr

We will require the context to handle RV64 word operations.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging

A large collection of RISC-V fixes, improvements and features

- Clenaup some left over v1.9 code
- D

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging

A large collection of RISC-V fixes, improvements and features

- Clenaup some left over v1.9 code
- Documentation improvements
- Support for the shakti_c machine
- Internal cleanup of the CSR accesses
- Updates to the OpenTitan platform
- Support for the virtio-vga
- Fix for the saturate subtract in vector extensions
- Experimental support for the ePMP spec
- A range of other internal code cleanups and bug fixes

# gpg: Signature made Tue 11 May 2021 11:17:10 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210511: (42 commits)
target/riscv: Fix the RV64H decode comment
target/riscv: Consolidate RV32/64 16-bit instructions
target/riscv: Consolidate RV32/64 32-bit instructions
target/riscv: Remove an unused CASE_OP_32_64 macro
target/riscv: Remove the unused HSTATUS_WPRI macro
target/riscv: Remove the hardcoded SATP_MODE macro
target/riscv: Remove the hardcoded MSTATUS_SD macro
target/riscv: Remove the hardcoded HGATP_MODE macro
target/riscv: Remove the hardcoded SSTATUS_SD macro
target/riscv: Remove the hardcoded RVXLEN macro
target/riscv: fix a typo with interrupt names
fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
hw/riscv: Fix OT IBEX reset vector
target/riscv: fix exception index on instruction access fault
target/riscv: fix vrgather macro index variable type bug
target/riscv: Add ePMP support for the Ibex CPU
target/riscv/pmp: Remove outdated comment
target/riscv: Add a config option for ePMP
target/riscv: Implementation of enhanced PMP (ePMP)
target/riscv: Add ePMP CSR access functions
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/riscv: Consolidate RV32/64 32-bit instructions

This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.

This m

target/riscv: Consolidate RV32/64 32-bit instructions

This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com

show more ...

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging

This fixes two bugs in the RISC-V port. One is a bug in the
Ibex PLIC, the other fixes the Hypvervisor

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging

This fixes two bugs in the RISC-V port. One is a bug in the
Ibex PLIC, the other fixes the Hypvervisor access functions.

# gpg: Signature made Tue 10 Nov 2020 03:53:49 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20201109:
hw/intc/ibex_plic: Clear the claim register when read
target/riscv: Split the Hypervisor execute load helpers
target/riscv: Remove the hyp load and store functions
target/riscv: Remove the HS_TWO_STAGE flag
target/riscv: Set the virtualised MMU mode when doing hyp accesses
target/riscv: Add a virtualised MMU Mode

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/riscv: Split the Hypervisor execute load helpers

Split the hypervisor execute load functions into two seperate functions.
This avoids us having to pass the memop to the C helper functions.

S

target/riscv: Split the Hypervisor execute load helpers

Split the hypervisor execute load functions into two seperate functions.
This avoids us having to pass the memop to the C helper functions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 5b1550f0faa3c435cc77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com

show more ...

target/riscv: Remove the hyp load and store functions

Remove the special Virtulisation load and store functions and just use
the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions

target/riscv: Remove the hyp load and store functions

Remove the special Virtulisation load and store functions and just use
the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions
instead.

As part of this change we ensure we still run an access check to make
sure we can perform the operations.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 189ac3e53ef2854824d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com

show more ...

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200825' into staging

This pull request first adds support for multi-socket NUMA RISC-V
machines. The Spike and Virt machines

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200825' into staging

This pull request first adds support for multi-socket NUMA RISC-V
machines. The Spike and Virt machines both support NUMA sockets.

This PR also updates the current experimental Hypervisor support to the
v0.6.1 spec.

# gpg: Signature made Tue 25 Aug 2020 19:47:41 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200825:
target/riscv: Support the Virtual Instruction fault
target/riscv: Return the exception from invalid CSR accesses
target/riscv: Support the v0.6 Hypervisor extension CRSs
target/riscv: Only support little endian guests
target/riscv: Only support a single VSXL length
target/riscv: Update the CSRs to the v0.6 Hyp extension
target/riscv: Update the Hypervisor trap return/entry
target/riscv: Fix the interrupt cause code
target/riscv: Convert MSTATUS MTL to GVA
target/riscv: Don't allow guest to write to htinst
target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
target/riscv: Allow generating hlv/hlvx/hsv instructions
target/riscv: Allow setting a two-stage lookup in the virt status
hw/riscv: virt: Allow creating multiple NUMA sockets
hw/riscv: spike: Allow creating multiple NUMA sockets
hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
hw/riscv: Allow creating multiple instances of PLIC
hw/riscv: Allow creating multiple instances of CLINT

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/riscv: Support the Virtual Instruction fault

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wd

target/riscv: Support the Virtual Instruction fault

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com
Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com>

show more ...

target/riscv: Allow generating hlv/hlvx/hsv instructions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.franc

target/riscv: Allow generating hlv/hlvx/hsv instructions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>

show more ...