Searched refs:REG_INDEX (Results 1 – 8 of 8) sorted by relevance
135 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro170 return s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_EN; in allwinner_a10_spi_is_enabled()176 s->regs[REG_INDEX(SPI_INT_STA_REG)] |= (SPI_INT_STA_TE | SPI_INT_STA_TE14 | in allwinner_a10_spi_txfifo_reset()178 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= ~(SPI_INT_STA_TU | SPI_INT_STA_TO); in allwinner_a10_spi_txfifo_reset()184 s->regs[REG_INDEX(SPI_INT_STA_REG)] &= in allwinner_a10_spi_rxfifo_reset()191 return (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_SS) >> SPI_CTL_SS_SHIFT; in allwinner_a10_spi_selected_channel()198 s->regs[REG_INDEX(SPI_RXDATA_REG)] = SPI_DATA_RESET; in allwinner_a10_spi_reset_hold()199 s->regs[REG_INDEX(SPI_TXDATA_REG)] = SPI_DATA_RESET; in allwinner_a10_spi_reset_hold()200 s->regs[REG_INDEX(SPI_CTL_REG)] = SPI_CTL_RESET; in allwinner_a10_spi_reset_hold()201 s->regs[REG_INDEX(SPI_INTCTL_REG)] = SPI_INTCTL_RESET; in allwinner_a10_spi_reset_hold()[all …]
59 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro107 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_ccu_read()123 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_ccu_write()171 s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; in allwinner_h3_ccu_reset()172 s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; in allwinner_h3_ccu_reset()173 s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; in allwinner_h3_ccu_reset()174 s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; in allwinner_h3_ccu_reset()175 s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; in allwinner_h3_ccu_reset()176 s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; in allwinner_h3_ccu_reset()177 s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; in allwinner_h3_ccu_reset()[all …]
59 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro71 const uint32_t idx = REG_INDEX(offset); in allwinner_r40_ccu_read()126 s->regs[REG_INDEX(offset)] = (uint32_t) val; in allwinner_r40_ccu_write()147 s->regs[REG_INDEX(REG_PLL_CPUX_CTRL)] = 0x00001000; in allwinner_r40_ccu_reset()148 s->regs[REG_INDEX(REG_PLL_AUDIO_CTRL)] = 0x00035514; in allwinner_r40_ccu_reset()149 s->regs[REG_INDEX(REG_PLL_VIDEO0_CTRL)] = 0x03006207; in allwinner_r40_ccu_reset()150 s->regs[REG_INDEX(REG_PLL_VE_CTRL)] = 0x03006207; in allwinner_r40_ccu_reset()151 s->regs[REG_INDEX(REG_PLL_DDR0_CTRL)] = 0x00001000, in allwinner_r40_ccu_reset()152 s->regs[REG_INDEX(REG_PLL_PERIPH0_CTRL)] = 0x00041811; in allwinner_r40_ccu_reset()153 s->regs[REG_INDEX(REG_PLL_PERIPH1_CTRL)] = 0x00041811; in allwinner_r40_ccu_reset()[all …]
51 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro77 const uint32_t idx = REG_INDEX(offset); in allwinner_a10_ccm_read()114 const uint32_t idx = REG_INDEX(offset); in allwinner_a10_ccm_write()163 s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST; in allwinner_a10_ccm_reset_enter()164 s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST; in allwinner_a10_ccm_reset_enter()165 s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST; in allwinner_a10_ccm_reset_enter()166 s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST; in allwinner_a10_ccm_reset_enter()167 s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST; in allwinner_a10_ccm_reset_enter()168 s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST; in allwinner_a10_ccm_reset_enter()169 s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST; in allwinner_a10_ccm_reset_enter()[all …]
38 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro60 const uint32_t idx = REG_INDEX(offset); in allwinner_a10_dramc_read()84 const uint32_t idx = REG_INDEX(offset); in allwinner_a10_dramc_write()99 s->regs[REG_INDEX(REG_SDR_ZQSR)] |= REG_SDR_ZQSR_ZCAL; in allwinner_a10_dramc_write()130 s->regs[REG_INDEX(REG_SDR_CCR)] = REG_SDR_CCR_RESET; in allwinner_a10_dramc_reset_enter()131 s->regs[REG_INDEX(REG_SDR_ZQCR0)] = REG_SDR_ZQCR0_RESET; in allwinner_a10_dramc_reset_enter()132 s->regs[REG_INDEX(REG_SDR_ZQSR)] = REG_SDR_ZQSR_RESET; in allwinner_a10_dramc_reset_enter()
34 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro46 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_sysctrl_read()61 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_sysctrl_write()94 s->regs[REG_INDEX(REG_VER)] = REG_VER_RST; in allwinner_h3_sysctrl_reset()95 s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST; in allwinner_h3_sysctrl_reset()
33 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro102 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_dramcom_read()119 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_dramcom_write()146 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_dramctl_read()163 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_dramctl_write()175 s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE; in allwinner_h3_dramctl_write()176 s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE; in allwinner_h3_dramctl_write()189 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_dramphy_read()206 const uint32_t idx = REG_INDEX(offset); in allwinner_h3_dramphy_write()
34 #define REG_INDEX(offset) (offset / sizeof(uint32_t)) macro185 const uint32_t idx = REG_INDEX(offset); in allwinner_r40_dramcom_read()201 const uint32_t idx = REG_INDEX(offset); in allwinner_r40_dramcom_write()228 const uint32_t idx = REG_INDEX(offset); in allwinner_r40_dramctl_read()244 const uint32_t idx = REG_INDEX(offset); in allwinner_r40_dramctl_write()256 s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE; in allwinner_r40_dramctl_write()257 s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE; in allwinner_r40_dramctl_write()268 const uint32_t idx = REG_INDEX(offset); in allwinner_r40_dramphy_read()284 const uint32_t idx = REG_INDEX(offset); in allwinner_r40_dramphy_write()381 reg = s->dramctl[REG_INDEX(REG_DRAMCTL_PGCR)]; in allwinner_r40_dualrank_detect_read()[all …]