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Searched refs:REGS (Results 1 – 25 of 42) sorted by relevance

12

/openbmc/linux/arch/hexagon/include/asm/
H A Delf.h91 #define CS_COPYREGS(DEST,REGS) \ argument
93 DEST.cs0 = REGS->cs0;\
94 DEST.cs1 = REGS->cs1;\
97 #define CS_COPYREGS(DEST,REGS) argument
100 #define ELF_CORE_COPY_REGS(DEST, REGS) \ argument
102 DEST.r0 = REGS->r00; \
103 DEST.r1 = REGS->r01; \
104 DEST.r2 = REGS->r02; \
105 DEST.r3 = REGS->r03; \
106 DEST.r4 = REGS->r04; \
[all …]
/openbmc/linux/arch/arm/probes/
H A Ddecode-arm.c156 REGS(0, NOPC, 0, 0, 0)),
163 REGS(0, 0, 0, 0, NOPC)),
167 REGS(0, NOPC, 0, 0, NOPC)),
174 REGS(NOPC, NOPC, 0, 0, NOPC)),
190 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
196 REGS(NOPC, 0, NOPC, 0, NOPC)),
202 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
213 REGS(NOPC, 0, NOPC, 0, NOPC)),
220 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
233 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
[all …]
H A Ddecode-thumb.c54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
59 REGS(NOSP, 0, 0, 0, NOSPPC)),
79 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
85 REGS(NOPC, 0, 0, 0, NOSPPC)),
90 REGS(0, 0, NOSPPC, 0, NOSPPC)),
105 REGS(SP, 0, SP, 0, NOSPPC)),
114 REGS(SP, 0, NOPC, 0, NOSPPC)),
128 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
139 REGS(NOSPPC, 0, 0, 0, 0)),
145 REGS(NOPC, 0, 0, 0, 0)),
[all …]
/openbmc/qemu/tcg/i386/
H A Dtcg-target-con-str.h12 REGS('a', 1u << TCG_REG_EAX)
13 REGS('b', 1u << TCG_REG_EBX)
14 REGS('c', 1u << TCG_REG_ECX)
15 REGS('d', 1u << TCG_REG_EDX)
16 REGS('S', 1u << TCG_REG_ESI)
17 REGS('D', 1u << TCG_REG_EDI)
19 REGS('r', ALL_GENERAL_REGS)
20 REGS('x', ALL_VECTOR_REGS)
21 REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
22 REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */
[all …]
/openbmc/qemu/tcg/arm/
H A Dtcg-target-con-str.h11 REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
12 REGS('r', ALL_GENERAL_REGS)
13 REGS('q', ALL_QLDST_REGS)
14 REGS('Q', ALL_QLDST_REGS & 0x5555) /* even qldst */
15 REGS('w', ALL_VECTOR_REGS)
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h295 #define REGS(_array, _sel_reg, _sel_val) \ macro
300 REGS(a6xx_registers, 0, 0),
301 REGS(a660_registers, 0, 0),
302 REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
303 REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
332 REGS(a6xx_ahb_registers, 0, 0),
336 REGS(a6xx_vbif_registers, 0, 0);
339 REGS(a6xx_gbif_registers, 0, 0);
381 REGS(a6xx_gmu_cx_registers, 0, 0),
382 REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dar0521.c675 #define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__})) macro
681 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
684 REGS(be(0x301E), be(0x00AA)),
687 REGS(be(0x3042),
691 REGS(be(0x30D2),
697 REGS(be(0x30DA),
703 REGS(be(0x30EE), be(0x1136)),
704 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
705 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
706 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
[all …]
/openbmc/qemu/tcg/ppc/
H A Dtcg-target-con-str.h11 REGS('r', ALL_GENERAL_REGS)
12 REGS('o', ALL_GENERAL_REGS & 0xAAAAAAAAu) /* odd registers */
13 REGS('v', ALL_VECTOR_REGS)
/openbmc/qemu/tcg/s390x/
H A Dtcg-target-con-str.h11 REGS('r', ALL_GENERAL_REGS)
12 REGS('v', ALL_VECTOR_REGS)
13 REGS('o', 0xaaaa) /* odd numbered general regs */
/openbmc/linux/drivers/video/fbdev/nvidia/
H A Dnv_setup.c295 par->PRAMIN = par->REGS + (0x00710000 / 4); in NVCommonSetup()
296 par->PCRTC0 = par->REGS + (0x00600000 / 4); in NVCommonSetup()
297 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); in NVCommonSetup()
298 par->PFB = par->REGS + (0x00100000 / 4); in NVCommonSetup()
299 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
300 par->PGRAPH = par->REGS + (0x00400000 / 4); in NVCommonSetup()
301 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
302 par->PTIMER = par->REGS + (0x00009000 / 4); in NVCommonSetup()
303 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
304 par->FIFO = par->REGS + (0x00800000 / 4); in NVCommonSetup()
[all …]
H A Dnvidia.c1203 volatile u32 __iomem *REGS) in nvidia_get_chipset() argument
1212 id = NV_RD32(REGS, 0x1800); in nvidia_get_chipset()
1282 volatile u32 __iomem *REGS; in nvidiafb_probe() local
1302 REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); in nvidiafb_probe()
1303 if (!REGS) { in nvidiafb_probe()
1308 Chipset = nvidia_get_chipset(pd, REGS); in nvidiafb_probe()
1347 par->REGS = REGS; in nvidiafb_probe()
1431 iounmap(REGS); in nvidiafb_probe()
1449 iounmap(par->REGS); in nvidiafb_remove()
/openbmc/qemu/target/hexagon/imported/
H A Dshift.idef30 #define RSHIFTTYPES(TAGEND,REGD,REGS,REGSTYPE,ACC,ACCSRC,SAT,SATOPT,ATTRS) \
31 Q6INSN(S2_asr_r_##TAGEND,#REGD "32" #ACC "=asr(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
35 REGD##V = SAT(ACCSRC ACC fBIDIR_ASHIFTR(REGS##V,shamt,REGSTYPE)); \
38 Q6INSN(S2_asl_r_##TAGEND,#REGD "32" #ACC "=asl(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
42 REGD##V = SAT(ACCSRC ACC fBIDIR_ASHIFTL(REGS##V,shamt,REGSTYPE)); \
45 Q6INSN(S2_lsr_r_##TAGEND,#REGD "32" #ACC "=lsr(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
49 REGD##V = SAT(ACCSRC ACC fBIDIR_LSHIFTR(REGS##V,shamt,REGSTYPE)); \
52 Q6INSN(S2_lsl_r_##TAGEND,#REGD "32" #ACC "=lsl(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
56 REGD##V = SAT(ACCSRC ACC fBIDIR_LSHIFTL(REGS##V,shamt,REGSTYPE)); \
76 #define RSATSHIFTTYPES(TAGEND,REGD,REGS,REGSTYPE) \
[all …]
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target-con-str.h11 REGS('r', ALL_GENERAL_REGS)
12 REGS('w', ALL_VECTOR_REGS)
/openbmc/qemu/tcg/riscv/
H A Dtcg-target-con-str.h11 REGS('r', ALL_GENERAL_REGS)
12 REGS('v', ALL_VECTOR_REGS)
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target-con-str.h16 REGS('r', ALL_GENERAL_REGS)
17 REGS('w', ALL_VECTOR_REGS)
/openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h43 #define REG(reg) (REGS)->offset.reg
45 #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
H A Ddmub_dcn301.c36 #define REGS dmub->regs macro
H A Ddmub_dcn21.c36 #define REGS dmub->regs macro
H A Ddmub_dcn303.c18 #define REGS dmub->regs macro
H A Ddmub_dcn302.c36 #define REGS dmub->regs macro
/openbmc/qemu/target/arm/
H A Dcpregs.h994 #define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ argument
996 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
997 define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \
998 ARRAY_SIZE(REGS)); \
1001 #define define_arm_cp_regs(CPU, REGS) \ argument
1002 define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
1030 #define modify_arm_cp_regs(REGS, MODS) \ argument
1032 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
1034 modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \
/openbmc/linux/arch/alpha/include/asm/
H A Delf.h114 #define ELF_CORE_COPY_REGS(DEST, REGS) \ argument
115 dump_elf_thread(DEST, REGS, current_thread_info());
/openbmc/qemu/tcg/tci/
H A Dtcg-target-con-str.h11 REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target-con-str.h11 REGS('r', ALL_GENERAL_REGS)
/openbmc/qemu/tcg/mips/
H A Dtcg-target-con-str.h11 REGS('r', ALL_GENERAL_REGS)

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