1abc730e1SRichard Henderson /* SPDX-License-Identifier: GPL-2.0-or-later */ 2abc730e1SRichard Henderson /* 3abc730e1SRichard Henderson * Define AArch64 target-specific operand constraints. 4abc730e1SRichard Henderson * Copyright (c) 2021 Linaro 5abc730e1SRichard Henderson */ 6abc730e1SRichard Henderson 7abc730e1SRichard Henderson /* 8abc730e1SRichard Henderson * Define constraint letters for register sets: 9abc730e1SRichard Henderson * REGS(letter, register_mask) 10abc730e1SRichard Henderson */ 11abc730e1SRichard Henderson REGS('r', ALL_GENERAL_REGS) 12abc730e1SRichard Henderson REGS('w', ALL_VECTOR_REGS) 13abc730e1SRichard Henderson 14abc730e1SRichard Henderson /* 15abc730e1SRichard Henderson * Define constraint letters for constants: 16abc730e1SRichard Henderson * CONST(letter, TCG_CT_CONST_* bit set) 17abc730e1SRichard Henderson */ 18abc730e1SRichard Henderson CONST('A', TCG_CT_CONST_AIMM) 19*339adf2fSRichard Henderson CONST('C', TCG_CT_CONST_CMP) 20abc730e1SRichard Henderson CONST('L', TCG_CT_CONST_LIMM) 21abc730e1SRichard Henderson CONST('M', TCG_CT_CONST_MONE) 22abc730e1SRichard Henderson CONST('O', TCG_CT_CONST_ORRI) 23abc730e1SRichard Henderson CONST('N', TCG_CT_CONST_ANDI) 24abc730e1SRichard Henderson CONST('Z', TCG_CT_CONST_ZERO) 25