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Searched refs:PPLL_CNTL (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/include/video/
H A Daty128.h243 #define PPLL_CNTL 0x0002 macro
H A Dradeon.h430 #define PPLL_CNTL 0x0002 macro
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_pm.c2265 OUTPLL(PPLL_CNTL, 0xa433);
2405 tmp = INPLL(PPLL_CNTL);
2406 OUTPLL(PPLL_CNTL, tmp);
2454 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2467 tmp = INPLL(PPLL_CNTL);
2468 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2470 tmp = INPLL(PPLL_CNTL);
2471 OUTPLL(PPLL_CNTL, tmp & ~0x1);
H A Daty128fb.c1026 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); in aty128_set_crtc()
1331 aty_st_pll(PPLL_CNTL, in aty128_set_pll()
1332 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); in aty128_set_pll()
1355 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); in aty128_set_pll()
H A Dradeon_base.c1381 OUTPLLP(PPLL_CNTL, in radeon_write_pll_regs()
1431 OUTPLLP(PPLL_CNTL, 0, in radeon_write_pll_regs()
/openbmc/qemu/hw/display/
H A Dati_regs.h288 #define PPLL_CNTL 0x02 macro
/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.c235 OUTPLLP(PPLL_CNTL, in radeon_write_pll_regs()
283 OUTPLLP(PPLL_CNTL, 0, in radeon_write_pll_regs()
/openbmc/u-boot/include/
H A Dradeon.h432 #define PPLL_CNTL 0x0002 macro