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Searched refs:PMB_DATA_BASE (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/board/renesas/sh7785lcr/
H A Dsh7785lcr.c42 writel(0, PMB_DATA_BASE(0)); in do_pmb()
44 writel(0, PMB_DATA_BASE(1)); in do_pmb()
46 writel(0, PMB_DATA_BASE(2)); in do_pmb()
50 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8)); in do_pmb()
52 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12)); in do_pmb()
H A Dlowlevel_init.S332 PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
333 PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
334 PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
335 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
336 PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
337 PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
338 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
339 PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
340 PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
/openbmc/u-boot/board/renesas/sh7752evb/
H A Dsh7752evb.c133 writel(0, PMB_DATA_BASE(0)); in set_pmb_on_board_init()
138 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); in set_pmb_on_board_init()
140 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); in set_pmb_on_board_init()
142 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); in set_pmb_on_board_init()
144 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); in set_pmb_on_board_init()
146 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); in set_pmb_on_board_init()
148 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); in set_pmb_on_board_init()
H A Dlowlevel_init.S427 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
428 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
429 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
/openbmc/u-boot/board/renesas/sh7753evb/
H A Dsh7753evb.c141 writel(0, PMB_DATA_BASE(0)); in set_pmb_on_board_init()
146 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); in set_pmb_on_board_init()
148 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); in set_pmb_on_board_init()
150 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); in set_pmb_on_board_init()
152 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); in set_pmb_on_board_init()
154 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); in set_pmb_on_board_init()
156 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); in set_pmb_on_board_init()
H A Dlowlevel_init.S396 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
397 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
398 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
/openbmc/u-boot/board/renesas/sh7757lcr/
H A Dsh7757lcr.c194 writel(0, PMB_DATA_BASE(0)); in set_pmb_on_board_init()
199 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); in set_pmb_on_board_init()
201 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); in set_pmb_on_board_init()
203 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); in set_pmb_on_board_init()
205 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); in set_pmb_on_board_init()
207 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); in set_pmb_on_board_init()
209 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); in set_pmb_on_board_init()
H A Dlowlevel_init.S526 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
527 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
528 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh4.h69 #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) macro