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Searched refs:PHASE_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/hw/scsi/
H A Dlsi53c895a.c182 #define PHASE_MASK 7 macro
329 return scsi_phases[phase & PHASE_MASK]; in scsi_phase_name()
571 s->sbcl &= ~PHASE_MASK; in lsi_set_phase()
573 s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase; in lsi_set_phase()
612 s->sstat1 &= ~PHASE_MASK; in lsi_disconnect()
688 p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO; in lsi_queue_command()
800 out = (s->sstat1 & PHASE_MASK) == PHASE_DO; in lsi_command_complete()
838 out = (s->sstat1 & PHASE_MASK) == PHASE_DO; in lsi_transfer_data()
1271 if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) { in lsi_execute_script()
1537 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7); in lsi_execute_script()
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/openbmc/linux/drivers/scsi/
H A DNCR5380.c354 (phases[i].value != (status & PHASE_MASK)); ++i) in NCR5380_print_phase()
810 if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) { in NCR5380_dma_complete()
1287 if ((NCR5380_read(STATUS_REG) & PHASE_MASK) != p) { in NCR5380_transfer_pio()
1361 *phase = tmp & PHASE_MASK; in NCR5380_transfer_pio()
1390 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); in do_reset()
1432 tmp = NCR5380_read(STATUS_REG) & PHASE_MASK; in do_abort()
1495 if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) { in NCR5380_transfer_dma()
1696 phase = (tmp & PHASE_MASK); in NCR5380_information_transfer()
H A DNCR5380.h173 #define PHASE_MASK (SR_MSG | SR_CD | SR_IO) macro
H A Dg_NCR5380.c128 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); in g_NCR5380_trigger_irq()
/openbmc/linux/drivers/scsi/aic7xxx/
H A Daic7xxx_reg_print.c_shipped62 { "PHASE_MASK", 0xe0, 0xe0 },
247 { "PHASE_MASK", 0xe0, 0xe0 },
H A Daic79xx_reg_print.c_shipped191 { "PHASE_MASK", 0xe0, 0xe0 }
673 { "PHASE_MASK", 0xe0, 0xe0 }
H A Daic7xxx.reg132 mask PHASE_MASK CDI|IOI|MSGI
163 mask PHASE_MASK CDI|IOI|MSGI
1508 mask PHASE_MASK CDI|IOI|MSGI
H A Daic7xxx_core.c1250 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; in ahc_handle_seqint()
1325 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; in ahc_handle_seqint()
1621 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; in ahc_handle_scsiint()
3127 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; in ahc_handle_proto_violation()
3218 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; in ahc_handle_message_phase()
H A Daic7xxx_reg.h_shipped460 #define PHASE_MASK 0xe0
H A Daic7xxx.seq1987 and LASTPHASE, PHASE_MASK, SCSISIGI;
2119 and SCSISIGO, PHASE_MASK, SCSISIGI;
2121 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
H A Daic79xx.reg1747 enum PHASE_MASK CDO|IOO|MSGO {
1778 enum PHASE_MASK CDO|IOO|MSGO {
3867 enum PHASE_MASK CDO|IOO|MSGO {
H A Daic79xx_core.c1888 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; in ahd_handle_seqint()
2063 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; in ahd_handle_seqint()
2692 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; in ahd_handle_transmission_error()
3303 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; in ahd_handle_proto_violation()
H A Daic79xx_reg.h_shipped1589 #define PHASE_MASK 0xe0
H A Daic79xx.seq1416 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1443 and LASTPHASE, PHASE_MASK, SCSISIGI;