Home
last modified time | relevance | path

Searched refs:PERI_ACLK_HZ (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c204 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
205 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
207 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
209 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
211 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
213 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()
364 return DIV_TO_RATE(PERI_ACLK_HZ, div); in rk3128_peri_get_pclk()
371 src_clk_div = PERI_ACLK_HZ / hz; in rk3128_peri_set_pclk()
388 return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div); in rk3128_peri_set_pclk()
H A Dclk_rk3036.c142 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
143 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
145 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
147 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
149 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
151 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()
H A Dclk_rk322x.c143 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
144 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
146 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
148 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
150 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
152 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()
H A Dclk_rk3188.c427 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
428 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
430 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
432 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
434 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
436 PERI_ACLK_HZ && (pclk_div < 0x4)); in rkclk_init()
H A Dclk_rk3288.c469 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
470 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
472 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
474 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
476 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
478 PERI_ACLK_HZ && (pclk_div < 0x4)); in rkclk_init()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h21 #define PERI_ACLK_HZ 148500000 macro
H A Dcru_rk3036.h22 #define PERI_ACLK_HZ 148500000 macro
H A Dcru_rk322x.h23 #define PERI_ACLK_HZ 148500000 macro
H A Dcru_rk3128.h24 #define PERI_ACLK_HZ 148500000 macro
H A Dcru_rk3288.h23 #define PERI_ACLK_HZ 148500000 macro