1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23f2ef139Shuang lin /* 33f2ef139Shuang lin * (C) Copyright 2015 Rockchip Electronics Co., Ltd 43f2ef139Shuang lin */ 53f2ef139Shuang lin #ifndef _ASM_ARCH_CRU_RK3036_H 63f2ef139Shuang lin #define _ASM_ARCH_CRU_RK3036_H 73f2ef139Shuang lin 83f2ef139Shuang lin #include <common.h> 93f2ef139Shuang lin 103f2ef139Shuang lin #define OSC_HZ (24 * 1000 * 1000) 113f2ef139Shuang lin 123f2ef139Shuang lin #define APLL_HZ (600 * 1000000) 133f2ef139Shuang lin #define GPLL_HZ (594 * 1000000) 143f2ef139Shuang lin 153f2ef139Shuang lin #define CORE_PERI_HZ 150000000 163f2ef139Shuang lin #define CORE_ACLK_HZ 300000000 173f2ef139Shuang lin 181960b010SKever Yang #define BUS_ACLK_HZ 148500000 191960b010SKever Yang #define BUS_HCLK_HZ 148500000 201960b010SKever Yang #define BUS_PCLK_HZ 74250000 213f2ef139Shuang lin 223f2ef139Shuang lin #define PERI_ACLK_HZ 148500000 233f2ef139Shuang lin #define PERI_HCLK_HZ 148500000 243f2ef139Shuang lin #define PERI_PCLK_HZ 74250000 253f2ef139Shuang lin 2692ac73e4SSimon Glass /* Private data for the clock driver - used by rockchip_get_cru() */ 2792ac73e4SSimon Glass struct rk3036_clk_priv { 2892ac73e4SSimon Glass struct rk3036_cru *cru; 2992ac73e4SSimon Glass ulong rate; 3092ac73e4SSimon Glass }; 3192ac73e4SSimon Glass 323f2ef139Shuang lin struct rk3036_cru { 333f2ef139Shuang lin struct rk3036_pll { 343f2ef139Shuang lin unsigned int con0; 353f2ef139Shuang lin unsigned int con1; 363f2ef139Shuang lin unsigned int con2; 373f2ef139Shuang lin unsigned int con3; 383f2ef139Shuang lin } pll[4]; 393f2ef139Shuang lin unsigned int cru_mode_con; 403f2ef139Shuang lin unsigned int cru_clksel_con[35]; 413f2ef139Shuang lin unsigned int cru_clkgate_con[11]; 423f2ef139Shuang lin unsigned int reserved; 433f2ef139Shuang lin unsigned int cru_glb_srst_fst_value; 443f2ef139Shuang lin unsigned int cru_glb_srst_snd_value; 453f2ef139Shuang lin unsigned int reserved1[2]; 463f2ef139Shuang lin unsigned int cru_softrst_con[9]; 473f2ef139Shuang lin unsigned int cru_misc_con; 483f2ef139Shuang lin unsigned int reserved2[2]; 493f2ef139Shuang lin unsigned int cru_glb_cnt_th; 503f2ef139Shuang lin unsigned int cru_sdmmc_con[2]; 513f2ef139Shuang lin unsigned int cru_sdio_con[2]; 523f2ef139Shuang lin unsigned int cru_emmc_con[2]; 533f2ef139Shuang lin unsigned int reserved3; 543f2ef139Shuang lin unsigned int cru_rst_st; 553f2ef139Shuang lin unsigned int reserved4[0x23]; 563f2ef139Shuang lin unsigned int cru_pll_mask_con; 573f2ef139Shuang lin }; 583f2ef139Shuang lin check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); 593f2ef139Shuang lin 603f2ef139Shuang lin struct pll_div { 613f2ef139Shuang lin u32 refdiv; 623f2ef139Shuang lin u32 fbdiv; 633f2ef139Shuang lin u32 postdiv1; 643f2ef139Shuang lin u32 postdiv2; 653f2ef139Shuang lin u32 frac; 663f2ef139Shuang lin }; 673f2ef139Shuang lin 683f2ef139Shuang lin enum { 693f2ef139Shuang lin /* PLLCON0*/ 703f2ef139Shuang lin PLL_POSTDIV1_SHIFT = 12, 7137943aaeSKever Yang PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 723f2ef139Shuang lin PLL_FBDIV_SHIFT = 0, 7337943aaeSKever Yang PLL_FBDIV_MASK = 0xfff, 743f2ef139Shuang lin 753f2ef139Shuang lin /* PLLCON1 */ 763f2ef139Shuang lin PLL_RST_SHIFT = 14, 7737943aaeSKever Yang PLL_DSMPD_SHIFT = 12, 7837943aaeSKever Yang PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 7937943aaeSKever Yang PLL_LOCK_STATUS_SHIFT = 10, 8037943aaeSKever Yang PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 8137943aaeSKever Yang PLL_POSTDIV2_SHIFT = 6, 8237943aaeSKever Yang PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 8337943aaeSKever Yang PLL_REFDIV_SHIFT = 0, 8437943aaeSKever Yang PLL_REFDIV_MASK = 0x3f, 853f2ef139Shuang lin 863f2ef139Shuang lin /* CRU_MODE */ 873f2ef139Shuang lin GPLL_MODE_SHIFT = 12, 8837943aaeSKever Yang GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 893f2ef139Shuang lin GPLL_MODE_SLOW = 0, 903f2ef139Shuang lin GPLL_MODE_NORM, 913f2ef139Shuang lin GPLL_MODE_DEEP, 923f2ef139Shuang lin DPLL_MODE_SHIFT = 4, 9337943aaeSKever Yang DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 943f2ef139Shuang lin DPLL_MODE_SLOW = 0, 953f2ef139Shuang lin DPLL_MODE_NORM, 963f2ef139Shuang lin APLL_MODE_SHIFT = 0, 9737943aaeSKever Yang APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 983f2ef139Shuang lin APLL_MODE_SLOW = 0, 993f2ef139Shuang lin APLL_MODE_NORM, 1003f2ef139Shuang lin 1013f2ef139Shuang lin /* CRU_CLK_SEL0_CON */ 10237943aaeSKever Yang BUS_ACLK_PLL_SEL_SHIFT = 14, 10337943aaeSKever Yang BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 10437943aaeSKever Yang BUS_ACLK_PLL_SEL_APLL = 0, 10537943aaeSKever Yang BUS_ACLK_PLL_SEL_DPLL, 10637943aaeSKever Yang BUS_ACLK_PLL_SEL_GPLL, 10737943aaeSKever Yang BUS_ACLK_DIV_SHIFT = 8, 10837943aaeSKever Yang BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 1093f2ef139Shuang lin CORE_CLK_PLL_SEL_SHIFT = 7, 11037943aaeSKever Yang CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 1113f2ef139Shuang lin CORE_CLK_PLL_SEL_APLL = 0, 1123f2ef139Shuang lin CORE_CLK_PLL_SEL_GPLL, 1133f2ef139Shuang lin CORE_DIV_CON_SHIFT = 0, 11437943aaeSKever Yang CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 1153f2ef139Shuang lin 1163f2ef139Shuang lin /* CRU_CLK_SEL1_CON */ 11737943aaeSKever Yang BUS_PCLK_DIV_SHIFT = 12, 11837943aaeSKever Yang BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 11937943aaeSKever Yang BUS_HCLK_DIV_SHIFT = 8, 12037943aaeSKever Yang BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 1213f2ef139Shuang lin CORE_ACLK_DIV_SHIFT = 4, 12237943aaeSKever Yang CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 1233f2ef139Shuang lin CORE_PERI_DIV_SHIFT = 0, 12437943aaeSKever Yang CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 1253f2ef139Shuang lin 1263f2ef139Shuang lin /* CRU_CLKSEL10_CON */ 1273f2ef139Shuang lin PERI_PLL_SEL_SHIFT = 14, 12837943aaeSKever Yang PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 1293f2ef139Shuang lin PERI_PLL_APLL = 0, 1303f2ef139Shuang lin PERI_PLL_DPLL, 1313f2ef139Shuang lin PERI_PLL_GPLL, 1323f2ef139Shuang lin PERI_PCLK_DIV_SHIFT = 12, 13337943aaeSKever Yang PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 1343f2ef139Shuang lin PERI_HCLK_DIV_SHIFT = 8, 13537943aaeSKever Yang PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 1363f2ef139Shuang lin PERI_ACLK_DIV_SHIFT = 0, 13737943aaeSKever Yang PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 1383f2ef139Shuang lin 1393f2ef139Shuang lin /* CRU_CLKSEL11_CON */ 1403f2ef139Shuang lin SDIO_DIV_SHIFT = 8, 14137943aaeSKever Yang SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, 1423f2ef139Shuang lin MMC0_DIV_SHIFT = 0, 14337943aaeSKever Yang MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, 1443f2ef139Shuang lin 1453f2ef139Shuang lin /* CRU_CLKSEL12_CON */ 1463f2ef139Shuang lin EMMC_PLL_SHIFT = 12, 14737943aaeSKever Yang EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 1483f2ef139Shuang lin EMMC_SEL_APLL = 0, 1493f2ef139Shuang lin EMMC_SEL_DPLL, 1503f2ef139Shuang lin EMMC_SEL_GPLL, 1513f2ef139Shuang lin EMMC_SEL_24M, 1523f2ef139Shuang lin SDIO_PLL_SHIFT = 10, 15337943aaeSKever Yang SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 1543f2ef139Shuang lin SDIO_SEL_APLL = 0, 1553f2ef139Shuang lin SDIO_SEL_DPLL, 1563f2ef139Shuang lin SDIO_SEL_GPLL, 1573f2ef139Shuang lin SDIO_SEL_24M, 1583f2ef139Shuang lin MMC0_PLL_SHIFT = 8, 15937943aaeSKever Yang MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 1603f2ef139Shuang lin MMC0_SEL_APLL = 0, 1613f2ef139Shuang lin MMC0_SEL_DPLL, 1623f2ef139Shuang lin MMC0_SEL_GPLL, 1633f2ef139Shuang lin MMC0_SEL_24M, 1643f2ef139Shuang lin EMMC_DIV_SHIFT = 0, 16537943aaeSKever Yang EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, 1663f2ef139Shuang lin 1673f2ef139Shuang lin /* CRU_SOFTRST5_CON */ 1683f2ef139Shuang lin DDRCTRL_PSRST_SHIFT = 11, 1693f2ef139Shuang lin DDRCTRL_SRST_SHIFT = 10, 1703f2ef139Shuang lin DDRPHY_PSRST_SHIFT = 9, 1713f2ef139Shuang lin DDRPHY_SRST_SHIFT = 8, 1723f2ef139Shuang lin }; 1733f2ef139Shuang lin #endif 174