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Searched refs:PCIE (Results 1 – 25 of 92) sorted by relevance

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/openbmc/u-boot/doc/
H A DREADME.srio-pcie-boot-corenet2 SRIO and PCIE Boot on Corenet Platforms
5 For some PowerPC processors with SRIO or PCIE interface, boot location can be
6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
8 from another processor's memory space by SRIO or PCIE link connected between
12 platforms and a RCW example with boot from SRIO or PCIE configuration.
14 Environment of the SRIO or PCIE boot:
16 b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
21 e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
22 the boot location to SRIO or PCIE, and holdoff all the cores.
27 | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
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/openbmc/qemu/docs/
H A Dpcie_pci_bridge.txt6 PCIE-to-PCI bridge is a new method for legacy PCI
12 PCIE-to-PCI bridge should now be used for any legacy PCI device usage
15 This generic PCIE-PCI bridge is a cross-platform device,
17 see 'PCIE-PCI bridge hot-plug' section),
25 PCIE-PCI bridge hot-plug
27 Guest OSes require extra efforts to enable PCIE-PCI bridge hot-plug.
36 that is planned to have PCIE-PCI bridge hot-plugged in.
89 - 2 PCIE-PCI bridges plugged into 2 different root ports;
92 - PCIE-PCI bridge, plugged into QEMU generic root port;
93 - 2 e1000 cards, one plugged into the cold-plugged PCIE-PCI bridge,
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c174 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
179 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up()
184 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); in comphy_pcie_power_up()
189 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
194 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); in comphy_pcie_power_up()
199 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up()
213 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
222 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, in comphy_pcie_power_up()
229 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
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H A Dcomphy_a3700.h74 PCIE = 1, enumerator
80 if (unit == PCIE) in phy_addr()
/openbmc/linux/Documentation/admin-guide/perf/
H A Dnvidia-pmu.rst12 * PCIE
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
63 PCIE device of the remote SoC.
122 The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
123 to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
139 traffic from remote GPU and PCIE devices.
160 PCIE PMU
163 The PCIE PMU monitors all read/write traffic from PCIE root ports to
201 * : PCIE : * * : PCIE : *
233 | Local | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU | CNVLink |
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/openbmc/u-boot/board/freescale/lx2160a/
H A DREADME88 1 |Mezzanine:X-M4-PCIE-SGMII (29733)
91 |Mezzanine:X-M4-PCIE-SGMII (29733)
98 |Mezzanine:X-M4-PCIE-SGMII (29733)
105 |Mezzanine:X-M4-PCIE-SGMII (29733)
126 |Mezzanine:X-M4-PCIE-SGMII (29733)
133 |Mezzanine:X-M4-PCIE-SGMII (29733)
155 2 |Mezzanine:X-M6-PCIE-X8 (29737) *
160 3 |Mezzanine:X-M4-PCIE-SGMII (29733)
163 |Mezzanine:X-M4-PCIE-SGMII (29733)
167 5 |Mezzanine:X-M4-PCIE-SGMII (29733)
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/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c703 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", in brcmf_pcie_reset_device()
774 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", in brcmf_pcie_send_mb_data()
813 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); in brcmf_pcie_handle_mb_data()
815 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); in brcmf_pcie_handle_mb_data()
817 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); in brcmf_pcie_handle_mb_data()
820 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); in brcmf_pcie_handle_mb_data()
822 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); in brcmf_pcie_handle_mb_data()
827 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n"); in brcmf_pcie_handle_mb_data()
932 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_quick_check_isr()
946 brcmf_dbg(PCIE, "Enter %x\n", status); in brcmf_pcie_isr_thread()
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H A DKconfig41 bool "PCIE bus interface support for FullMAC driver"
47 This option enables the PCIE bus interface support for Broadcom
49 use the driver for an PCIE wireless card.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/aer-inject/
H A Daer-inject_1.0.bb1 SUMMARY = "Inject PCIE AER errors on the software level into a running Linux kernel."
3 aer-inject allows to inject PCIE AER errors on the software \
5 validation of the PCIE driver error recovery handler and \
6 PCIE AER core handler."
/openbmc/linux/drivers/phy/amlogic/
H A DKconfig64 tristate "Meson G12A USB3+PCIE Combo PHY driver"
70 Enable this to support the Meson USB3 + PCIE Combo PHY found
75 tristate "Meson AXG PCIE PHY driver"
81 Enable this to support the Meson MIPI + PCIE PHY found
86 tristate "Meson AXG MIPI + PCIE analog PHY driver"
93 Enable this to support the Meson MIPI + PCIE analog PHY
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dchip_registers.h20 #define PCIE 0 macro
584 #define PCI_CFG_MSIX0 (PCIE + 0x0000000000B0)
585 #define PCI_CFG_REG1 (PCIE + 0x000000000004)
586 #define PCI_CFG_REG11 (PCIE + 0x00000000002C)
587 #define PCIE_CFG_SPCIE1 (PCIE + 0x00000000014C)
588 #define PCIE_CFG_SPCIE2 (PCIE + 0x000000000150)
589 #define PCIE_CFG_TPH2 (PCIE + 0x000000000180)
1269 #define PCIE_CFG_REG_PL2 (PCIE + 0x000000000708)
1270 #define PCIE_CFG_REG_PL3 (PCIE + 0x00000000070C)
1273 #define PCIE_CFG_REG_PL102 (PCIE + 0x000000000898)
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/openbmc/linux/drivers/phy/st/
H A Dphy-spear1310-miphy.c98 PCIE, enumerator
156 if (priv->mode == PCIE) in spear1310_miphy_init()
167 if (priv->mode == PCIE) in spear1310_miphy_exit()
197 if (priv->mode != SATA && priv->mode != PCIE) { in spear1310_miphy_xlate()
H A Dphy-spear1340-miphy.c77 PCIE, enumerator
164 else if (priv->mode == PCIE) in spear1340_miphy_init()
177 else if (priv->mode == PCIE) in spear1340_miphy_exit()
234 if (priv->mode != SATA && priv->mode != PCIE) { in spear1340_miphy_xlate()
/openbmc/linux/drivers/net/ethernet/huawei/hinic/
H A DKconfig7 tristate "Huawei Intelligent PCIE Network Interface Card"
11 This driver supports HiNIC PCIE Ethernet cards.
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dpinmux.c263 PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
264 PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
265 PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
266 PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
267 PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
268 PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
269 PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
270 PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
271 PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
272 PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
/openbmc/u-boot/board/nvidia/cardhu/
H A Dpinmux-config-cardhu.h267 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
272 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
273 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
274 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
275 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
276 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h263 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
264 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
265 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
266 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
267 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
272 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dmarvell-8xxx.txt1 Marvell 8787/8897/8978/8997 (sd8787/sd8897/sd8978/sd8997/pcie8997) SDIO/PCIE devices
4 This node provides properties for controlling the Marvell SDIO/PCIE wireless device.
5 The node is expected to be specified as a child node to the SDIO/PCIE controller that
/openbmc/linux/drivers/soc/loongson/
H A DKconfig11 The global utilities block controls PCIE device enabling, alternate
13 and PCIE, configuration of memory controller, rtc controller, lio
/openbmc/linux/drivers/phy/freescale/
H A DKconfig31 tristate "Freescale i.MX8M PCIE PHY"
35 Enable this to add support for the PCIE PHY as found on
/openbmc/linux/Documentation/translations/zh_CN/mm/
H A Dhmm.rst67 如果我们只考虑 PCIE 总线，那么设备可以访问主内存（通常通过 IOMMU）并与 CPU 缓存一
72 另一个严重的因素是带宽有限（约 32GBytes/s，PCIE 4.0 和 16 通道）。这比最快的 GPU
76 一些平台正在开发新的 I/O 总线或对 PCIE 的添加/修改以解决其中一些限制
/openbmc/u-boot/board/toradex/colibri_t30/
H A Dpinmux-config-colibri_t30.h279 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
284 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
285 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
286 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
287 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
288 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
289 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
290 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-mba6.dtsi94 /* PCIE.PWR_EN */
495 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
496 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
497 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
525 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A DREADME23 * PCIE slot and mini-PCIE slots
/openbmc/openbmc-test-automation/redfish/telemetry_service/
H A Dtest_telemetry_report.robot19 &{user_tele_def} ambient temperature=Ambient.*Temp pcie temperature=PCIE.*Temp
62 Verify Basic Telemetry Report Creation For PCIE
63 [Documentation] Verify basic telemetry report creations for PCIE.

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