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Searched refs:MXL_RV64 (Results 1 – 12 of 12) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dgdbstub.c68 case MXL_RV64: in riscv_cpu_gdb_read_register()
90 case MXL_RV64: in riscv_cpu_gdb_write_register()
92 if (env->xl < MXL_RV64) { in riscv_cpu_gdb_write_register()
354 case MXL_RV64: in riscv_cpu_register_gdb_regs_for_features()
H A Ddebug.c83 case MXL_RV64: in extract_trigger_type()
142 case MXL_RV64: in build_tdata1()
190 case MXL_RV64: in tdata1_validate()
239 case MXL_RV64: in textra_validate()
268 case MXL_RV64: in textra_validate()
383 case MXL_RV64: in trigger_textra_match()
423 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_breakpoint_size()
462 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_mcontrol_validate()
H A Dtranslate.c134 #define get_xl(ctx) MXL_RV64
142 #define get_address_xl(ctx) MXL_RV64
355 case MXL_RV64: in get_gpr()
396 case MXL_RV64: in gen_set_gpr()
417 case MXL_RV64: in gen_set_gpri()
459 case MXL_RV64: in get_fpr_hs()
484 case MXL_RV64: in get_fpr_d()
506 case MXL_RV64: in dest_fpr()
529 case MXL_RV64: in gen_set_fpr_hs()
556 case MXL_RV64: in gen_set_fpr_d()
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H A Dcpu.c1048 case MXL_RV64: in riscv_cpu_disas_set_info()
1422 case MXL_RV64: in riscv_cpu_validate_misa_mxl()
2174 case MXL_RV64: in prop_marchid_set()
2727 case MXL_RV64: in riscv_gdb_arch_name()
2961 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
2980 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
2981 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
2982 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
2983 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
2984 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
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H A Dcpu_bits.h575 MXL_RV64 = 2, enumerator
H A Dcsr.c569 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { in pmp()
725 case MXL_RV64: in read_vtype()
1520 case MXL_RV64: in add_status_sd()
1698 case MXL_RV64: in read_misa()
1699 misa = (target_ulong)MXL_RV64 << 62; in read_misa()
2381 if (riscv_cpu_mxl(env) == MXL_RV64) { in write_menvcfg()
2491 if (riscv_cpu_mxl(env) == MXL_RV64) { in write_henvcfg()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzicfiss.c.inc26 uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4;
52 int tmp = (get_xl(ctx) == MXL_RV64) ? -8 : -4;
H A Dtrans_rvm.c.inc366 ctx->ol = MXL_RV64;
374 ctx->ol = MXL_RV64;
382 ctx->ol = MXL_RV64;
390 ctx->ol = MXL_RV64;
398 ctx->ol = MXL_RV64;
H A Dtrans_rvi.c.inc468 ctx->ol = MXL_RV64;
475 ctx->ol = MXL_RV64;
482 ctx->ol = MXL_RV64;
775 ctx->ol = MXL_RV64;
782 ctx->ol = MXL_RV64;
789 ctx->ol = MXL_RV64;
831 ctx->ol = MXL_RV64;
838 ctx->ol = MXL_RV64;
845 ctx->ol = MXL_RV64;
H A Dtrans_rvzacas.c.inc92 case MXL_RV64:
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c70 case MXL_RV64: in kvm_riscv_reg_id_ulong()
1992 mcc->misa_mxl_max = MXL_RV64; in riscv_host_cpu_class_init()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1143 if (cpu->env.misa_mxl != MXL_RV64) { in cpu_set_profile()