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Searched refs:MDIO_MMD_AN (Results 1 – 25 of 38) sorted by relevance

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/openbmc/linux/drivers/net/phy/
H A Dphy-c45.c238 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, in genphy_c45_baset1_an_config_aneg()
247 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, in genphy_c45_baset1_an_config_aneg()
285 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
296 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
345 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
369 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
403 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
424 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
477 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_baset1_read_lpa()
[all …]
H A Dbcm84881.c101 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in bcm84881_config_aneg()
117 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_aneg_done()
121 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_aneg_done()
134 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in bcm84881_read_status()
143 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_read_status()
147 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_read_status()
173 val = phy_read_mmd(phydev, MDIO_MMD_AN, in bcm84881_read_status()
H A Dadin1100.c78 ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS); in adin_read_status()
111 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
114 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
120 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
129 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
H A Daquantia_main.c273 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, in aqr_config_aneg()
293 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); in aqr_config_intr()
298 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr()
316 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); in aqr_config_intr()
328 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, in aqr_handle_interrupt()
348 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); in aqr_read_status()
368 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); in aqr107_read_rate()
473 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); in aqr107_get_downshift()
497 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, in aqr107_set_downshift()
620 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); in aqr107_link_change_notify()
[all …]
H A Drealtek.c598 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { in rtlgen_read_mmd()
602 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { in rtlgen_read_mmd()
618 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { in rtlgen_write_mmd()
640 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { in rtl822x_read_mmd()
644 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { in rtl822x_read_mmd()
661 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { in rtl822x_write_mmd()
H A Dteranetics.c62 reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in teranetics_read_status()
H A Dbcm-phy-lib.c377 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL); in bcm_phy_set_eee()
386 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); in bcm_phy_set_eee()
389 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV); in bcm_phy_set_eee()
405 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); in bcm_phy_set_eee()
512 { "phy_lpi_count", MDIO_MMD_AN, BRCM_CL45VEN_EEE_LPI_CNT, 0, 16 },
H A Dmarvell10g.c623 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
629 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN, in mv2110_set_mactype()
637 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
901 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, in mv3310_config_aneg()
989 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in mv3310_read_status_copper()
1046 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); in mv3310_read_status_copper()
H A Dmediatek-ge.c27 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in mtk_gephy_config_init()
H A Dat803x.c972 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, in at803x_clk_out_config()
1330 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in at803x_config_aneg()
1609 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); in qca83xx_config_init()
1714 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, in qca808x_phy_fast_retrain_config()
1811 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in qca808x_read_status()
2033 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); in qca808x_get_features()
H A Dmarvell-88q2xxx.c55 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT); in mv88q2xxx_read_link_gbit()
/openbmc/u-boot/drivers/net/phy/
H A Daquantia.c321 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1); in aquantia_config()
322 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440); in aquantia_config()
352 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
353 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
359 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
371 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
372 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
400 MDIO_MMD_PHYXS | MDIO_MMD_AN |
413 MDIO_MMD_PHYXS | MDIO_MMD_AN |
426 MDIO_MMD_PHYXS | MDIO_MMD_AN |
[all …]
H A Dteranetics.c32 phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); in tn2020_config()
/openbmc/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in xgbe_an73_clear_interrupts()
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in xgbe_an73_disable_interrupts()
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); in xgbe_an73_enable_interrupts()
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an73_set()
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an73_set()
493 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_an73_tx_training()
494 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_an73_tx_training()
532 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); in xgbe_an73_tx_xnp()
533 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); in xgbe_an73_tx_xnp()
534 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); in xgbe_an73_tx_xnp()
[all …]
H A Dxgbe-phy-v1.c243 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an_outcome()
244 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an_outcome()
267 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an_outcome()
268 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an_outcome()
291 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an_outcome()
292 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an_outcome()
/openbmc/linux/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c85 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
87 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value); in vfio_platform_amdxgbe_reset()
90 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in vfio_platform_amdxgbe_reset()
93 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INT, 0); in vfio_platform_amdxgbe_reset()
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c134 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_enable()
147 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_restart()
162 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in aq100x_advertise()
173 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, AQ_1G_CTRL, in aq100x_advertise()
188 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in aq100x_advertise()
223 err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v); in aq100x_get_link_status()
/openbmc/linux/drivers/net/ethernet/sfc/falcon/
H A Dmdio_10g.c55 if (mmd != MDIO_MMD_AN) { in ef4_mdio_check_mmd()
285 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); in ef4_mdio_an_reconfigure()
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); in ef4_mdio_an_reconfigure()
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); in ef4_mdio_an_reconfigure()
307 ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA)); in ef4_mdio_get_pause()
H A Dtenxpress.c263 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); in sfx7101_check_bad_lp()
446 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); in tenxpress_get_link_ksettings()
449 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in tenxpress_get_link_ksettings()
473 ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in sfx7101_set_npage_adv()
/openbmc/linux/drivers/net/
H A Dmdio.c142 mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1, in mdio45_nway_restart()
153 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr); in mdio45_get_an()
259 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, in mdio45_ethtool_gset_npage()
277 MDIO_MMD_AN, MDIO_STAT1); in mdio45_ethtool_gset_npage()
430 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, in mdio45_ethtool_ksettings_get_npage()
448 MDIO_MMD_AN, MDIO_STAT1); in mdio45_ethtool_ksettings_get_npage()
574 devad = MDIO_MMD_AN; in mdio_mii_ioctl()
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1118 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1142 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1160 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1165 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1340 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1348 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
[all …]
H A Dixgbe_x550.c1931 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_check_link_t_X550em()
2388 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2395 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2438 MDIO_MMD_AN, &reg); in ixgbe_enable_lasi_ext_t_x550em()
2446 MDIO_MMD_AN, reg); in ixgbe_enable_lasi_ext_t_x550em()
2613 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_ext_phy_t_x550em_get_link()
2618 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_ext_phy_t_x550em_get_link()
2665 MDIO_MMD_AN, in ixgbe_setup_internal_phy_t_x550em()
2829 MDIO_MMD_AN, in ixgbe_get_lcd_t_x550em()
3065 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
[all …]
/openbmc/u-boot/include/linux/
H A Dmdio.h24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ macro
123 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
/openbmc/linux/drivers/net/pcs/
H A Dpcs-xpcs.c439 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); in _xpcs_config_aneg_c73()
452 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); in _xpcs_config_aneg_c73()
463 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); in _xpcs_config_aneg_c73()
475 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); in xpcs_config_aneg_c73()
481 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); in xpcs_config_aneg_c73()
491 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); in xpcs_aneg_done_c73()
522 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); in xpcs_read_lpa_c73()
963 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); in xpcs_get_state_c73()
/openbmc/linux/include/uapi/linux/
H A Dmdio.h25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ macro
154 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)

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