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Searched refs:MAX_CS (Results 1 – 16 of 16) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dxor.c17 static u32 xor_regs_base_backup[MAX_CS];
18 static u32 xor_regs_mask_backup[MAX_CS];
28 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()
30 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()
50 for (ui = 0; ui < MAX_CS; ui++) { in mv_sys_xor_init()
89 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()
91 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()
H A Dddr3_spd.c191 extern u16 odt_static[ODT_OPT][MAX_CS];
192 extern u16 odt_dynamic[ODT_OPT][MAX_CS];
646 if (cs_num > MAX_CS) {
648 MAX_CS, 1);
661 for (cs = 0; cs < MAX_CS; cs += 2) {
683 MAX_CS, 1);
896 for (cs = 0; cs < MAX_CS; cs++) {
920 for (cs = 0; cs < MAX_CS; cs++) {
936 for (cs = 0; cs < MAX_CS; cs++) {
1013 for (cs = 0; cs < MAX_CS; cs++) {
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H A Dddr3_write_leveling.c52 extern u16 odt_static[ODT_OPT][MAX_CS];
53 extern u16 odt_dynamic[ODT_OPT][MAX_CS];
106 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
228 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
430 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
529 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
618 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
660 u32 res[MAX_CS]; in ddr3_write_leveling_sw()
678 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
718 memset(dram_info->wl_val, 0, sizeof(u32) * MAX_CS * MAX_PUP_NUM * 7); in ddr3_write_leveling_sw()
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H A Dddr3_dfs.c43 extern u16 odt_dynamic[ODT_OPT][MAX_CS];
47 extern u16 odt_static[ODT_OPT][MAX_CS];
195 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
441 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
467 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
675 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
1004 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1136 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1162 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1435 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
H A Dddr3_axp_vars.h41 u16 odt_static[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
60 u16 odt_dynamic[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
H A Dddr3_init.c168 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
184 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
231 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_and_set_training_windows()
1076 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_cs_num_from_reg()
H A Dddr3_axp.h16 #define MAX_CS 4 macro
438 #define MAX_CS 4 macro
H A Dddr3_hw_training.h259 u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
260 u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
H A Dddr3_dqs.c150 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_rx()
232 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_tx()
1334 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_load_dqs_patterns()
H A Dddr3_hw_training.c715 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_training()
1027 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_min_max_read_sample_delay()
H A Dddr3_read_leveling.c97 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
H A Dddr3_pbs.c1559 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_load_pbs_patterns()
/openbmc/linux/drivers/net/ethernet/pasemi/
H A Dpasemi_mac.h23 #define MAX_CS 2 macro
78 struct pasemi_mac_csring *cs[MAX_CS];
H A Dpasemi_mac.c349 for (i = 0; i < MAX_CS; i++) in pasemi_mac_setup_csrings()
/openbmc/linux/drivers/mtd/nand/raw/
H A Dintel-nand-controller.c103 #define MAX_CS 2 macro
124 struct ebu_nand_cs cs[MAX_CS];
613 if (cs >= MAX_CS) { in ebu_nand_probe()
/openbmc/linux/drivers/spi/
H A Dspi-microchip-core.c24 #define MAX_CS (1) macro
536 num_cs = MAX_CS; in mchp_corespi_probe()