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Searched refs:MASK (Results 1 – 25 of 154) sorted by relevance

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/openbmc/linux/drivers/iommu/intel/
H A Dcap_audit.h67 #define DO_CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \ argument
70 intel_iommu_##cap##_sanity &= ~(MASK); \
75 #define CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \ argument
76 DO_CHECK_FEATURE_MISMATCH((a)->cap, (b)->cap, cap, feature, MASK)
78 #define CHECK_FEATURE_MISMATCH_HOTPLUG(b, cap, feature, MASK) \ argument
82 (b)->cap, cap, feature, MASK); \
85 #define MINIMAL_FEATURE_IOMMU(iommu, cap, MASK) \ argument
87 u64 min_feature = intel_iommu_##cap##_sanity & (MASK); \
88 min_feature = min_t(u64, min_feature, (iommu)->cap & (MASK)); \
89 intel_iommu_##cap##_sanity = (intel_iommu_##cap##_sanity & ~(MASK)) | \
[all …]
/openbmc/linux/include/linux/soc/ti/
H A Dknav_dma.h17 #define MASK(x) (BIT(x) - 1) macro
18 #define KNAV_DMA_DESC_PKT_LEN_MASK MASK(22)
22 #define KNAV_DMA_DESC_TAG_MASK MASK(8)
30 #define KNAV_DMA_DESC_PSLEN_MASK MASK(6)
32 #define KNAV_DMA_DESC_ERR_FLAG_MASK MASK(4)
34 #define KNAV_DMA_DESC_PSFLAG_MASK MASK(4)
36 #define KNAV_DMA_DESC_RETQ_MASK MASK(14)
37 #define KNAV_DMA_DESC_BUF_LEN_MASK MASK(22)
38 #define KNAV_DMA_DESC_EFLAGS_MASK MASK(4)
/openbmc/linux/sound/soc/codecs/
H A Dak4613.c425 #define MASK(x) (1 << AK4613_CHANNEL_##x) in ak4613_hw_constraints() macro
428 [AK4613_CONFIG_MODE_STEREO] = { MASK(2), MASK(2), MASK(2), MASK(2)}, in ak4613_hw_constraints()
429 [AK4613_CONFIG_MODE_TDM512] = { MASK(4), MASK(12), MASK(12), MASK(12)}, in ak4613_hw_constraints()
430 [AK4613_CONFIG_MODE_TDM256] = { MASK(4), MASK(8), MASK(8)|MASK(12), MASK(8)|MASK(12)}, in ak4613_hw_constraints()
431 [AK4613_CONFIG_MODE_TDM128] = { MASK(4), MASK(4), MASK(4)|MASK(8), MASK(4)|MASK(8)|MASK(12)}, in ak4613_hw_constraints()
/openbmc/u-boot/board/micronas/vct/
H A Dgpio.c22 #define MASK(pin) (1 << ((pin) & 0x1F)) macro
46 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); in vct_gpio_dir()
48 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); in vct_gpio_dir()
60 clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); in vct_gpio_set()
62 clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); in vct_gpio_set()
73 return ((value & MASK(pin)) ? 1 : 0); in vct_gpio_get()
/openbmc/linux/arch/x86/kernel/cpu/mce/
H A Dseverity.c66 #define MASK(x, y) .mask = x, .result = y macro
115 SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
119 SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
130 SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0),
137 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
142 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
158 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
163 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
168 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
173 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.h30 #define MASK(w) ((1 << (w)) - 1) macro
49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
87 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
92 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
H A Dgm20b.c41 (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT)
45 (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT)
53 (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT)
57 (MASK(GPCPLL_DVFS0_DFS_DET_MAX_WIDTH) << GPCPLL_DVFS0_DFS_DET_MAX_SHIFT)
169 MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_pllg_read_mnp()
201 dvfs->dfs_coeff = min_t(u32, coeff, MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH)); in gm20b_dvfs_calc_det_coeff()
254 rem = ((u32)n) & MASK(DFS_DET_RANGE); in gm20b_dvfs_calc_ndiv()
259 *sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_dvfs_calc_ndiv()
536 nvkm_mask(device, GPC_BCAST_GPCPLL_DVFS2, MASK(DFS_DET_RANGE + 1), in gm20b_dvfs_program_ext_cal()
788 data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH); in gm20b_clk_init_dvfs()
[all …]
/openbmc/linux/arch/arm/mach-rpc/
H A Dirq.c15 #define MASK 0x08 macro
130 val = readb(base + MASK); in iomd_irq_mask_ack()
131 writeb(val & ~mask, base + MASK); in iomd_irq_mask_ack()
140 val = readb(base + MASK); in iomd_irq_mask()
141 writeb(val & ~mask, base + MASK); in iomd_irq_mask()
149 val = readb(base + MASK); in iomd_irq_unmask()
150 writeb(val | mask, base + MASK); in iomd_irq_unmask()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
164 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
168 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
172 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
/openbmc/linux/arch/x86/crypto/
H A Dpoly1305-x86_64-cryptogams.pl419 my ($H0,$H1,$H2,$H3,$H4, $T0,$T1,$T2,$T3,$T4, $D0,$D1,$D2,$D3,$D4, $MASK) =
888 vmovdqa 64(%rcx),$MASK # .Lmask26
898 vpand $MASK,$T0,$T0 # 0
900 vpand $MASK,$T1,$T1 # 1
902 vpand $MASK,$T2,$T2 # 2
903 vpand $MASK,$T3,$T3 # 3
1052 vpand $MASK,$H0,$H0 # 0
1054 vpand $MASK,$H1,$H1 # 1
1057 vpand $MASK,$H2,$H2 # 2
1058 vpand $MASK,$H3,$H3 # 3
[all …]
/openbmc/linux/drivers/scsi/sym53c8xx_2/
H A Dsym_fw2.h228 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
316 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
348 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
438 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
462 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
521 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
681 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
898 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
904 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1073 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
H A Dsym_fw1.h236 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
363 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
453 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
478 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
538 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
704 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
949 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
955 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1187 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1207 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dtest_pkt_md_access.c11 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
14 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
19 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
23 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
/openbmc/qemu/include/qemu/
H A Dlog.h53 #define qemu_log_mask(MASK, FMT, ...) \ argument
55 if (unlikely(qemu_loglevel_mask(MASK))) { \
67 #define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \ argument
69 if (unlikely(qemu_loglevel_mask(MASK)) && \
/openbmc/linux/include/linux/irqchip/
H A Darm-gic-v3.h181 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
183 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
208 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
210 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
277 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
279 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
315 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
317 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
419 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
421 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
[all …]
/openbmc/u-boot/test/lib/
H A Dstring.c19 #define MASK 0xA5 macro
83 ptr = memset(buf + offset, MASK, len); in lib_memset()
85 if (test_memset(uts, buf, MASK, offset, len)) { in lib_memset()
138 init_buffer(buf1, MASK); in lib_memcpy()
147 if (test_memmove(uts, buf2, MASK, offset1, in lib_memcpy()
/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h48 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ argument
51 if (MASK) { \
68 #define fGETQBITS(REG, WIDTH, MASK, BITNO) \ argument
69 ((MASK) & (REG.w[(BITNO) >> 5] >> ((BITNO) & 0x1f)))
94 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
97 REG.w[(BITNO) >> 5] &= ~((MASK) << ((BITNO) & 0x1f)); \
98 REG.w[(BITNO) >> 5] |= (((__TMP) & (MASK)) << ((BITNO) & 0x1f)); \
108 #define fV_AL_CHECK(EA, MASK) \ argument
109 if ((EA) & (MASK)) { \
293 #define fSTOREMMVQ(EA, SRC, MASK) \ argument
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dpoly1305-armv4.pl497 my ($T0,$T1,$MASK) = map("q$_",(15,4,0));
1101 vorn $MASK,$MASK,$MASK @ all-ones, can be redundant
1103 vshr.u64 $MASK,$MASK,#38
1145 vorn $MASK,$MASK,$MASK @ all-ones
1147 vshr.u64 $MASK,$MASK,#38
1166 vand.i64 $D3,$D3,$MASK
1168 vand.i64 $D0,$D0,$MASK
1173 vand.i64 $D4,$D4,$MASK
1175 vand.i64 $D1,$D1,$MASK
1181 vand.i64 $D2,$D2,$MASK
[all …]
H A Dghash-ce-core.S59 MASK .req d28
163 vmull.p64 T1, XL_L, MASK
170 vmull.p64 XL, T1_H, MASK
229 vmov.i8 MASK, #0xe1
230 vshl.u64 MASK, MASK, #57
298 vmov.i8 MASK, #0xe1
299 vshl.u64 MASK, MASK, #57
341 vmov.i8 MASK, #0xe1
342 vshl.u64 MASK, MASK, #57
601 vmov.i8 MASK, #0xe1
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dpoly1305-armv8.pl267 my ($T0,$T1,$MASK) = map("v$_",(29..31));
542 movi $MASK.2d,#-1
546 ushr $MASK.2d,$MASK.2d,#38
708 and $ACC0,$ACC0,$MASK.2d
848 and $ACC3,$ACC3,$MASK.2d
850 and $ACC0,$ACC0,$MASK.2d
856 and $ACC4,$ACC4,$MASK.2d
858 and $ACC1,$ACC1,$MASK.2d
864 and $ACC2,$ACC2,$MASK.2d
869 and $ACC0,$ACC0,$MASK.2d
[all …]
/openbmc/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h13 #define MASK(x) (BIT(x) - 1) macro
17 #define FRM_END_START_MASK MASK(2)
50 #define CH_OVLY_SEL_MASK MASK(2)
99 #define QOSGENERATOR_MODE_MASK MASK(2)
/openbmc/qemu/include/hw/rtc/
H A Dxlnx-zynqmp-rtc.h67 FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1)
69 FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1)
71 FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1)
/openbmc/qemu/target/arm/tcg/
H A Diwmmxt_helper.c299 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
300 (TYPE) ((b >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
305 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
306 (TYPE) ((b >> SHR) & MASK)) ? a : b) & ((uint64_t) MASK << SHR))
312 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
313 OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
318 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
319 OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
/openbmc/linux/net/openvswitch/
H A Ddatapath.h277 #define OVS_MASKED(OLD, KEY, MASK) ((KEY) | ((OLD) & ~(MASK))) argument
278 #define OVS_SET_MASKED(OLD, KEY, MASK) ((OLD) = OVS_MASKED(OLD, KEY, MASK)) argument
/openbmc/qemu/hw/scsi/
H A Dvmw_pvscsi.h30 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
372 #define PVSCSI_INTR_CMPL_MASK MASK(2)
376 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
378 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)

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