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Searched refs:INSN (Results 1 – 16 of 16) sorted by relevance

/openbmc/qemu/target/avr/
H A Ddisas.c96 #define INSN(opcode, format, ...) \ macro
133 INSN(ADD, "r%d, r%d", a->rd, a->rr)
134 INSN(ADC, "r%d, r%d", a->rd, a->rr)
135 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
136 INSN(SUB, "r%d, r%d", a->rd, a->rr)
137 INSN(SUBI, "r%d, %d", a->rd, a->imm)
138 INSN(SBC, "r%d, r%d", a->rd, a->rr)
139 INSN(SBCI, "r%d, %d", a->rd, a->imm)
140 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
141 INSN(AND, "r%d, r%d", a->rd, a->rr)
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/openbmc/qemu/target/openrisc/
H A Ddisas.c53 #define INSN(opcode, format, ...) \ macro
60 INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b)
61 INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b)
62 INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b)
63 INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b)
64 INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b)
65 INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b)
66 INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b)
67 INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b)
68 INSN(sra, "r%d, r%d, r%d", a->d, a->a, a->b)
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/openbmc/qemu/target/loongarch/
H A Ddisas.c123 #define output(C, INSN, FMT, ...) \ argument
127 (C)->insn, INSN, ##__VA_ARGS__); \
130 INSN, ##__VA_ARGS__); \
349 #define INSN(insn, type) \ macro
356 INSN(clo_w, rr) in INSN() function
357 INSN(clz_w, rr) in INSN()
358 INSN(cto_w, rr) in INSN()
359 INSN(ctz_w, rr) in INSN()
360 INSN(clo_d, rr) in INSN()
361 INSN(clz_d, rr) in INSN()
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/openbmc/qemu/tests/tcg/hexagon/
H A Dusr.c51 #define FUNC_x_OP_x(RESTYPE, SRCTYPE, NAME, INSN) \ argument
57 INSN "\n\t" \
66 #define FUNC_R_OP_R(NAME, INSN) \ argument
67 FUNC_x_OP_x(uint32_t, uint32_t, NAME, INSN)
69 #define FUNC_R_OP_P(NAME, INSN) \ argument
70 FUNC_x_OP_x(uint32_t, uint64_t, NAME, INSN)
72 #define FUNC_P_OP_P(NAME, INSN) \ argument
73 FUNC_x_OP_x(uint64_t, uint64_t, NAME, INSN)
75 #define FUNC_P_OP_R(NAME, INSN) \ argument
76 FUNC_x_OP_x(uint64_t, uint32_t, NAME, INSN)
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/openbmc/qemu/target/m68k/
H A Dtranslate.c5774 #define INSN(name, opcode, mask, feature) do { \ in register_m68k_insns() macro
5779 INSN(arith_im, 0080, fff8, CF_ISA_A); in register_m68k_insns()
5780 INSN(arith_im, 0000, ff00, M68K); in register_m68k_insns()
5781 INSN(chk2, 00c0, f9c0, CHK2); in register_m68k_insns()
5782 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); in register_m68k_insns()
5787 INSN(movep, 0108, f138, MOVEP); in register_m68k_insns()
5788 INSN(arith_im, 0280, fff8, CF_ISA_A); in register_m68k_insns()
5789 INSN(arith_im, 0200, ff00, M68K); in register_m68k_insns()
5790 INSN(undef, 02c0, ffc0, M68K); in register_m68k_insns()
5791 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); in register_m68k_insns()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-mve.c531 #define DO_1OP_VEC(INSN, FN, VECFN) \ argument
532 static bool trans_##INSN(DisasContext *s, arg_1op *a) \
543 #define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL) argument
558 #define DO_VCVT(INSN, HFN, SFN) \ in DO_1OP() argument
559 static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ in DO_1OP()
563 static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \
567 static bool trans_##INSN(DisasContext *s, arg_1op *a) \
571 gen_##INSN##h, \
572 gen_##INSN##s, \
620 #define DO_VCVT_RMODE(INSN, RMODE, U) \ argument
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H A Dtranslate-neon.c809 #define DO_3SAME(INSN, FUNC) \ argument
810 static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
836 #define DO_3SAME_BITSEL(INSN, O1, O2, O3) \ in DO_3SAME() argument
837 static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ in DO_3SAME()
843 DO_3SAME(INSN, gen_##INSN##_3s)
849 #define DO_3SAME_NO_SZ_3(INSN, FUNC) \ argument
850 static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
882 #define DO_3SAME_CMP(INSN, COND) \ argument
883 static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
889 DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
[all …]
H A Dmve_helper.c1810 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ argument
1811 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \
1812 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \
1813 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC)
1815 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ argument
1816 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \
1817 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \
1818 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC)
1913 #define DO_VMAXMINV_U(INSN, FN) \ argument
1914 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \
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H A Dtranslate-vfp.c2255 #define MAKE_ONE_VFM_TRANS_FN(INSN, PREC, NEGN, NEGD) \ argument
2256 static bool trans_##INSN##_##PREC(DisasContext *s, \
2257 arg_##INSN##_##PREC *a) \
2393 #define DO_VFP_2OP(INSN, PREC, FN, CHECK) \ argument
2394 static bool trans_##INSN##_##PREC(DisasContext *s, \
2395 arg_##INSN##_##PREC *a) \
2403 #define DO_VFP_VMOV(INSN, PREC, FN) \ argument
2404 static bool trans_##INSN##_##PREC(DisasContext *s, \
2405 arg_##INSN##_##PREC *a) \
/openbmc/qemu/tests/tcg/ppc64/
H A Dnon_signalling_xscv.c6 #define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \ argument
12 INSN " 32, 32\n\t" \
19 printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \
H A Dvsx_f2i_nan.c11 #define DEFINE_VSX_F2I_FUNC(SRC_T, DEST_T, INSN) \ argument
16 asm(#INSN " %x0, %x1" : "=wa" (result) : "wa" (v)); \
/openbmc/qemu/tests/tcg/hppa/
H A Dstby.c41 #define TEST(INSN, OFS, E) \ argument
44 asm volatile(INSN " %1, " #OFS "(%0)" \
46 check(&s, E, which, INSN, OFS); \
/openbmc/linux/arch/sparc/kernel/
H A Dvisemul.c136 #define RS1(INSN) (((INSN) >> 14) & 0x1f) argument
137 #define RS2(INSN) (((INSN) >> 0) & 0x1f) argument
138 #define RD(INSN) (((INSN) >> 25) & 0x1f) argument
/openbmc/linux/arch/loongarch/include/asm/
H A Dinst.h33 #define ADDR_IMM(addr, INSN) \ argument
34 (sign_extend64(((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN), ADDR_IMMSBIDX_##INSN))
/openbmc/qemu/disas/
H A Dsparc.c2265 #define HASH_INSN(INSN) \ argument
2266 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
/openbmc/linux/tools/perf/
H A Dbuiltin-script.c1513 if (PRINT_FIELD(INSN) && sample->insn_len) { in perf_sample__fprintf_insn()