1*d18b0652SJohn Platts #include <stdio.h>
2*d18b0652SJohn Platts #include "qemu/compiler.h"
3*d18b0652SJohn Platts
4*d18b0652SJohn Platts typedef vector float vsx_float32_vec_t;
5*d18b0652SJohn Platts typedef vector double vsx_float64_vec_t;
6*d18b0652SJohn Platts typedef vector signed int vsx_int32_vec_t;
7*d18b0652SJohn Platts typedef vector unsigned int vsx_uint32_vec_t;
8*d18b0652SJohn Platts typedef vector signed long long vsx_int64_vec_t;
9*d18b0652SJohn Platts typedef vector unsigned long long vsx_uint64_vec_t;
10*d18b0652SJohn Platts
11*d18b0652SJohn Platts #define DEFINE_VSX_F2I_FUNC(SRC_T, DEST_T, INSN) \
12*d18b0652SJohn Platts static inline vsx_##DEST_T##_vec_t \
13*d18b0652SJohn Platts vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(vsx_##SRC_T##_vec_t v) \
14*d18b0652SJohn Platts { \
15*d18b0652SJohn Platts vsx_##DEST_T##_vec_t result; \
16*d18b0652SJohn Platts asm(#INSN " %x0, %x1" : "=wa" (result) : "wa" (v)); \
17*d18b0652SJohn Platts return result; \
18*d18b0652SJohn Platts }
19*d18b0652SJohn Platts
DEFINE_VSX_F2I_FUNC(float32,int32,xvcvspsxws)20*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float32, int32, xvcvspsxws)
21*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float32, uint32, xvcvspuxws)
22*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float32, int64, xvcvspsxds)
23*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float32, uint64, xvcvspuxds)
24*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float64, int32, xvcvdpsxws)
25*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float64, uint32, xvcvdpuxws)
26*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float64, int64, xvcvdpsxds)
27*d18b0652SJohn Platts DEFINE_VSX_F2I_FUNC(float64, uint64, xvcvdpuxds)
28*d18b0652SJohn Platts
29*d18b0652SJohn Platts static inline vsx_float32_vec_t vsx_float32_is_nan(vsx_float32_vec_t v)
30*d18b0652SJohn Platts {
31*d18b0652SJohn Platts vsx_float32_vec_t abs_v;
32*d18b0652SJohn Platts vsx_float32_vec_t result_mask;
33*d18b0652SJohn Platts const vsx_uint32_vec_t f32_pos_inf_bits = {0x7F800000U, 0x7F800000U,
34*d18b0652SJohn Platts 0x7F800000U, 0x7F800000U};
35*d18b0652SJohn Platts
36*d18b0652SJohn Platts asm("xvabssp %x0, %x1" : "=wa" (abs_v) : "wa" (v));
37*d18b0652SJohn Platts asm("vcmpgtuw %0, %1, %2"
38*d18b0652SJohn Platts : "=v" (result_mask)
39*d18b0652SJohn Platts : "v" (abs_v), "v" (f32_pos_inf_bits));
40*d18b0652SJohn Platts return result_mask;
41*d18b0652SJohn Platts }
42*d18b0652SJohn Platts
vsx_float64_is_nan(vsx_float64_vec_t v)43*d18b0652SJohn Platts static inline vsx_float64_vec_t vsx_float64_is_nan(vsx_float64_vec_t v)
44*d18b0652SJohn Platts {
45*d18b0652SJohn Platts vsx_float64_vec_t abs_v;
46*d18b0652SJohn Platts vsx_float64_vec_t result_mask;
47*d18b0652SJohn Platts const vsx_uint64_vec_t f64_pos_inf_bits = {0x7FF0000000000000ULL,
48*d18b0652SJohn Platts 0x7FF0000000000000ULL};
49*d18b0652SJohn Platts
50*d18b0652SJohn Platts asm("xvabsdp %x0, %x1" : "=wa" (abs_v) : "wa" (v));
51*d18b0652SJohn Platts asm("vcmpgtud %0, %1, %2"
52*d18b0652SJohn Platts : "=v" (result_mask)
53*d18b0652SJohn Platts : "v" (abs_v), "v" (f64_pos_inf_bits));
54*d18b0652SJohn Platts return result_mask;
55*d18b0652SJohn Platts }
56*d18b0652SJohn Platts
57*d18b0652SJohn Platts #define DEFINE_VSX_BINARY_LOGICAL_OP_INSN(LANE_TYPE, OP_NAME, OP_INSN) \
58*d18b0652SJohn Platts static inline vsx_##LANE_TYPE##_vec_t vsx_##LANE_TYPE##_##OP_NAME( \
59*d18b0652SJohn Platts vsx_##LANE_TYPE##_vec_t a, vsx_##LANE_TYPE##_vec_t b) \
60*d18b0652SJohn Platts { \
61*d18b0652SJohn Platts vsx_##LANE_TYPE##_vec_t result; \
62*d18b0652SJohn Platts asm(#OP_INSN " %x0, %x1, %x2" : "=wa" (result) : "wa" (a), "wa" (b)); \
63*d18b0652SJohn Platts return result; \
64*d18b0652SJohn Platts }
65*d18b0652SJohn Platts
DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32,logical_and,xxland)66*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_and, xxland)
67*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_and, xxland)
68*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int32, logical_and, xxland)
69*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint32, logical_and, xxland)
70*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_and, xxland)
71*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint64, logical_and, xxland)
72*d18b0652SJohn Platts
73*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_andc, xxlandc)
74*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_andc, xxlandc)
75*d18b0652SJohn Platts
76*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_or, xxlor)
77*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_or, xxlor)
78*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int32, logical_or, xxlor)
79*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint32, logical_or, xxlor)
80*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_or, xxlor)
81*d18b0652SJohn Platts DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint64, logical_or, xxlor)
82*d18b0652SJohn Platts
83*d18b0652SJohn Platts static inline vsx_int32_vec_t vsx_mask_out_float32_vec_to_int32_vec(
84*d18b0652SJohn Platts vsx_int32_vec_t v)
85*d18b0652SJohn Platts {
86*d18b0652SJohn Platts return v;
87*d18b0652SJohn Platts }
vsx_mask_out_float32_vec_to_uint32_vec(vsx_uint32_vec_t v)88*d18b0652SJohn Platts static inline vsx_uint32_vec_t vsx_mask_out_float32_vec_to_uint32_vec(
89*d18b0652SJohn Platts vsx_uint32_vec_t v)
90*d18b0652SJohn Platts {
91*d18b0652SJohn Platts return v;
92*d18b0652SJohn Platts }
vsx_mask_out_float32_vec_to_int64_vec(vsx_int64_vec_t v)93*d18b0652SJohn Platts static inline vsx_int64_vec_t vsx_mask_out_float32_vec_to_int64_vec(
94*d18b0652SJohn Platts vsx_int64_vec_t v)
95*d18b0652SJohn Platts {
96*d18b0652SJohn Platts return v;
97*d18b0652SJohn Platts }
vsx_mask_out_float32_vec_to_uint64_vec(vsx_uint64_vec_t v)98*d18b0652SJohn Platts static inline vsx_uint64_vec_t vsx_mask_out_float32_vec_to_uint64_vec(
99*d18b0652SJohn Platts vsx_uint64_vec_t v)
100*d18b0652SJohn Platts {
101*d18b0652SJohn Platts return v;
102*d18b0652SJohn Platts }
103*d18b0652SJohn Platts
vsx_mask_out_float64_vec_to_int32_vec(vsx_int32_vec_t v)104*d18b0652SJohn Platts static inline vsx_int32_vec_t vsx_mask_out_float64_vec_to_int32_vec(
105*d18b0652SJohn Platts vsx_int32_vec_t v)
106*d18b0652SJohn Platts {
107*d18b0652SJohn Platts #if HOST_BIG_ENDIAN
108*d18b0652SJohn Platts const vsx_int32_vec_t valid_lanes_mask = {-1, 0, -1, 0};
109*d18b0652SJohn Platts #else
110*d18b0652SJohn Platts const vsx_int32_vec_t valid_lanes_mask = {0, -1, 0, -1};
111*d18b0652SJohn Platts #endif
112*d18b0652SJohn Platts
113*d18b0652SJohn Platts return vsx_int32_logical_and(v, valid_lanes_mask);
114*d18b0652SJohn Platts }
115*d18b0652SJohn Platts
vsx_mask_out_float64_vec_to_uint32_vec(vsx_uint32_vec_t v)116*d18b0652SJohn Platts static inline vsx_uint32_vec_t vsx_mask_out_float64_vec_to_uint32_vec(
117*d18b0652SJohn Platts vsx_uint32_vec_t v)
118*d18b0652SJohn Platts {
119*d18b0652SJohn Platts return (vsx_uint32_vec_t)vsx_mask_out_float64_vec_to_int32_vec(
120*d18b0652SJohn Platts (vsx_int32_vec_t)v);
121*d18b0652SJohn Platts }
122*d18b0652SJohn Platts
vsx_mask_out_float64_vec_to_int64_vec(vsx_int64_vec_t v)123*d18b0652SJohn Platts static inline vsx_int64_vec_t vsx_mask_out_float64_vec_to_int64_vec(
124*d18b0652SJohn Platts vsx_int64_vec_t v)
125*d18b0652SJohn Platts {
126*d18b0652SJohn Platts return v;
127*d18b0652SJohn Platts }
vsx_mask_out_float64_vec_to_uint64_vec(vsx_uint64_vec_t v)128*d18b0652SJohn Platts static inline vsx_uint64_vec_t vsx_mask_out_float64_vec_to_uint64_vec(
129*d18b0652SJohn Platts vsx_uint64_vec_t v)
130*d18b0652SJohn Platts {
131*d18b0652SJohn Platts return v;
132*d18b0652SJohn Platts }
133*d18b0652SJohn Platts
print_vsx_float32_vec_elements(FILE * stream,vsx_float32_vec_t vec)134*d18b0652SJohn Platts static inline void print_vsx_float32_vec_elements(FILE *stream,
135*d18b0652SJohn Platts vsx_float32_vec_t vec)
136*d18b0652SJohn Platts {
137*d18b0652SJohn Platts fprintf(stream, "%g, %g, %g, %g", (double)vec[0], (double)vec[1],
138*d18b0652SJohn Platts (double)vec[2], (double)vec[3]);
139*d18b0652SJohn Platts }
140*d18b0652SJohn Platts
print_vsx_float64_vec_elements(FILE * stream,vsx_float64_vec_t vec)141*d18b0652SJohn Platts static inline void print_vsx_float64_vec_elements(FILE *stream,
142*d18b0652SJohn Platts vsx_float64_vec_t vec)
143*d18b0652SJohn Platts {
144*d18b0652SJohn Platts fprintf(stream, "%.17g, %.17g", vec[0], vec[1]);
145*d18b0652SJohn Platts }
146*d18b0652SJohn Platts
print_vsx_int32_vec_elements(FILE * stream,vsx_int32_vec_t vec)147*d18b0652SJohn Platts static inline void print_vsx_int32_vec_elements(FILE *stream,
148*d18b0652SJohn Platts vsx_int32_vec_t vec)
149*d18b0652SJohn Platts {
150*d18b0652SJohn Platts fprintf(stream, "%d, %d, %d, %d", vec[0], vec[1], vec[2], vec[3]);
151*d18b0652SJohn Platts }
152*d18b0652SJohn Platts
print_vsx_uint32_vec_elements(FILE * stream,vsx_uint32_vec_t vec)153*d18b0652SJohn Platts static inline void print_vsx_uint32_vec_elements(FILE *stream,
154*d18b0652SJohn Platts vsx_uint32_vec_t vec)
155*d18b0652SJohn Platts {
156*d18b0652SJohn Platts fprintf(stream, "%u, %u, %u, %u", vec[0], vec[1], vec[2], vec[3]);
157*d18b0652SJohn Platts }
158*d18b0652SJohn Platts
print_vsx_int64_vec_elements(FILE * stream,vsx_int64_vec_t vec)159*d18b0652SJohn Platts static inline void print_vsx_int64_vec_elements(FILE *stream,
160*d18b0652SJohn Platts vsx_int64_vec_t vec)
161*d18b0652SJohn Platts {
162*d18b0652SJohn Platts fprintf(stream, "%lld, %lld", vec[0], vec[1]);
163*d18b0652SJohn Platts }
164*d18b0652SJohn Platts
print_vsx_uint64_vec_elements(FILE * stream,vsx_uint64_vec_t vec)165*d18b0652SJohn Platts static inline void print_vsx_uint64_vec_elements(FILE *stream,
166*d18b0652SJohn Platts vsx_uint64_vec_t vec)
167*d18b0652SJohn Platts {
168*d18b0652SJohn Platts fprintf(stream, "%llu, %llu", vec[0], vec[1]);
169*d18b0652SJohn Platts }
170*d18b0652SJohn Platts
171*d18b0652SJohn Platts #define DEFINE_VSX_ALL_EQ_FUNC(LANE_TYPE, CMP_INSN) \
172*d18b0652SJohn Platts static inline int vsx_##LANE_TYPE##_all_eq(vsx_##LANE_TYPE##_vec_t a, \
173*d18b0652SJohn Platts vsx_##LANE_TYPE##_vec_t b) \
174*d18b0652SJohn Platts { \
175*d18b0652SJohn Platts unsigned result; \
176*d18b0652SJohn Platts vsx_##LANE_TYPE##_vec_t is_eq_mask_vec; \
177*d18b0652SJohn Platts asm(#CMP_INSN ". %0, %2, %3\n\t" \
178*d18b0652SJohn Platts "mfocrf %1, 2" \
179*d18b0652SJohn Platts : "=v" (is_eq_mask_vec), "=r" (result) \
180*d18b0652SJohn Platts : "v" (a), "v" (b) \
181*d18b0652SJohn Platts : "cr6"); \
182*d18b0652SJohn Platts return (int)((result >> 7) & 1u); \
183*d18b0652SJohn Platts }
184*d18b0652SJohn Platts
DEFINE_VSX_ALL_EQ_FUNC(int32,vcmpequw)185*d18b0652SJohn Platts DEFINE_VSX_ALL_EQ_FUNC(int32, vcmpequw)
186*d18b0652SJohn Platts DEFINE_VSX_ALL_EQ_FUNC(uint32, vcmpequw)
187*d18b0652SJohn Platts DEFINE_VSX_ALL_EQ_FUNC(int64, vcmpequd)
188*d18b0652SJohn Platts DEFINE_VSX_ALL_EQ_FUNC(uint64, vcmpequd)
189*d18b0652SJohn Platts
190*d18b0652SJohn Platts #define DEFINE_VSX_F2I_TEST_FUNC(SRC_T, DEST_T) \
191*d18b0652SJohn Platts static inline int test_vsx_conv_##SRC_T##_vec_to_##DEST_T##_vec( \
192*d18b0652SJohn Platts vsx_##SRC_T##_vec_t src_v) \
193*d18b0652SJohn Platts { \
194*d18b0652SJohn Platts const vsx_##SRC_T##_vec_t is_nan_mask = vsx_##SRC_T##_is_nan(src_v); \
195*d18b0652SJohn Platts const vsx_##SRC_T##_vec_t nan_src_v = \
196*d18b0652SJohn Platts vsx_##SRC_T##_logical_and(src_v, is_nan_mask); \
197*d18b0652SJohn Platts const vsx_##SRC_T##_vec_t non_nan_src_v = \
198*d18b0652SJohn Platts vsx_##SRC_T##_logical_andc(src_v, is_nan_mask); \
199*d18b0652SJohn Platts \
200*d18b0652SJohn Platts const vsx_##DEST_T##_vec_t expected_result = \
201*d18b0652SJohn Platts vsx_mask_out_##SRC_T##_vec_to_##DEST_T##_vec( \
202*d18b0652SJohn Platts vsx_##DEST_T##_logical_or( \
203*d18b0652SJohn Platts vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(nan_src_v), \
204*d18b0652SJohn Platts vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec( \
205*d18b0652SJohn Platts non_nan_src_v))); \
206*d18b0652SJohn Platts const vsx_##DEST_T##_vec_t actual_result = \
207*d18b0652SJohn Platts vsx_mask_out_##SRC_T##_vec_to_##DEST_T##_vec( \
208*d18b0652SJohn Platts vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(src_v)); \
209*d18b0652SJohn Platts const int test_result = \
210*d18b0652SJohn Platts vsx_##DEST_T##_all_eq(expected_result, actual_result); \
211*d18b0652SJohn Platts \
212*d18b0652SJohn Platts if (unlikely(test_result == 0)) { \
213*d18b0652SJohn Platts fputs("FAIL: Conversion of " #SRC_T " vector to " #DEST_T \
214*d18b0652SJohn Platts " vector failed\n", stdout); \
215*d18b0652SJohn Platts fputs("Source values: ", stdout); \
216*d18b0652SJohn Platts print_vsx_##SRC_T##_vec_elements(stdout, src_v); \
217*d18b0652SJohn Platts fputs("\nExpected result: ", stdout); \
218*d18b0652SJohn Platts print_vsx_##DEST_T##_vec_elements(stdout, expected_result); \
219*d18b0652SJohn Platts fputs("\nActual result: ", stdout); \
220*d18b0652SJohn Platts print_vsx_##DEST_T##_vec_elements(stdout, actual_result); \
221*d18b0652SJohn Platts fputs("\n\n", stdout); \
222*d18b0652SJohn Platts } \
223*d18b0652SJohn Platts \
224*d18b0652SJohn Platts return test_result; \
225*d18b0652SJohn Platts }
226*d18b0652SJohn Platts
227*d18b0652SJohn Platts
228*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float32, int32)
229*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float32, uint32)
230*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float32, int64)
231*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float32, uint64)
232*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float64, int32)
233*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float64, uint32)
234*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float64, int64)
235*d18b0652SJohn Platts DEFINE_VSX_F2I_TEST_FUNC(float64, uint64)
236*d18b0652SJohn Platts
237*d18b0652SJohn Platts static inline vsx_int32_vec_t vsx_int32_vec_from_mask(int mask)
238*d18b0652SJohn Platts {
239*d18b0652SJohn Platts const vsx_int32_vec_t bits_to_test = {1, 2, 4, 8};
240*d18b0652SJohn Platts const vsx_int32_vec_t vec_mask = {mask, mask, mask, mask};
241*d18b0652SJohn Platts vsx_int32_vec_t result;
242*d18b0652SJohn Platts
243*d18b0652SJohn Platts asm("vcmpequw %0, %1, %2"
244*d18b0652SJohn Platts : "=v" (result)
245*d18b0652SJohn Platts : "v" (vsx_int32_logical_and(vec_mask, bits_to_test)),
246*d18b0652SJohn Platts "v" (bits_to_test));
247*d18b0652SJohn Platts return result;
248*d18b0652SJohn Platts }
249*d18b0652SJohn Platts
vsx_int64_vec_from_mask(int mask)250*d18b0652SJohn Platts static inline vsx_int64_vec_t vsx_int64_vec_from_mask(int mask)
251*d18b0652SJohn Platts {
252*d18b0652SJohn Platts const vsx_int64_vec_t bits_to_test = {1, 2};
253*d18b0652SJohn Platts const vsx_int64_vec_t vec_mask = {mask, mask};
254*d18b0652SJohn Platts vsx_int64_vec_t result;
255*d18b0652SJohn Platts
256*d18b0652SJohn Platts asm("vcmpequd %0, %1, %2"
257*d18b0652SJohn Platts : "=v" (result)
258*d18b0652SJohn Platts : "v" (vsx_int64_logical_and(vec_mask, bits_to_test)),
259*d18b0652SJohn Platts "v" (bits_to_test));
260*d18b0652SJohn Platts return result;
261*d18b0652SJohn Platts }
262*d18b0652SJohn Platts
main(void)263*d18b0652SJohn Platts int main(void)
264*d18b0652SJohn Platts {
265*d18b0652SJohn Platts const vsx_float32_vec_t f32_iota1 = {1.0f, 2.0f, 3.0f, 4.0f};
266*d18b0652SJohn Platts const vsx_float64_vec_t f64_iota1 = {1.0, 2.0};
267*d18b0652SJohn Platts
268*d18b0652SJohn Platts int num_of_tests_failed = 0;
269*d18b0652SJohn Platts
270*d18b0652SJohn Platts for (int i = 0; i < 16; i++) {
271*d18b0652SJohn Platts const vsx_int32_vec_t nan_mask = vsx_int32_vec_from_mask(i);
272*d18b0652SJohn Platts const vsx_float32_vec_t f32_v =
273*d18b0652SJohn Platts vsx_float32_logical_or(f32_iota1, (vsx_float32_vec_t)nan_mask);
274*d18b0652SJohn Platts num_of_tests_failed +=
275*d18b0652SJohn Platts (int)(!test_vsx_conv_float32_vec_to_int32_vec(f32_v));
276*d18b0652SJohn Platts num_of_tests_failed +=
277*d18b0652SJohn Platts (int)(!test_vsx_conv_float32_vec_to_int64_vec(f32_v));
278*d18b0652SJohn Platts num_of_tests_failed +=
279*d18b0652SJohn Platts (int)(!test_vsx_conv_float32_vec_to_uint32_vec(f32_v));
280*d18b0652SJohn Platts num_of_tests_failed +=
281*d18b0652SJohn Platts (int)(!test_vsx_conv_float32_vec_to_uint64_vec(f32_v));
282*d18b0652SJohn Platts }
283*d18b0652SJohn Platts
284*d18b0652SJohn Platts for (int i = 0; i < 4; i++) {
285*d18b0652SJohn Platts const vsx_int64_vec_t nan_mask = vsx_int64_vec_from_mask(i);
286*d18b0652SJohn Platts const vsx_float64_vec_t f64_v =
287*d18b0652SJohn Platts vsx_float64_logical_or(f64_iota1, (vsx_float64_vec_t)nan_mask);
288*d18b0652SJohn Platts num_of_tests_failed +=
289*d18b0652SJohn Platts (int)(!test_vsx_conv_float64_vec_to_int32_vec(f64_v));
290*d18b0652SJohn Platts num_of_tests_failed +=
291*d18b0652SJohn Platts (int)(!test_vsx_conv_float64_vec_to_int64_vec(f64_v));
292*d18b0652SJohn Platts num_of_tests_failed +=
293*d18b0652SJohn Platts (int)(!test_vsx_conv_float64_vec_to_uint32_vec(f64_v));
294*d18b0652SJohn Platts num_of_tests_failed +=
295*d18b0652SJohn Platts (int)(!test_vsx_conv_float64_vec_to_uint64_vec(f64_v));
296*d18b0652SJohn Platts }
297*d18b0652SJohn Platts
298*d18b0652SJohn Platts printf("%d tests failed\n", num_of_tests_failed);
299*d18b0652SJohn Platts return (int)(num_of_tests_failed != 0);
300*d18b0652SJohn Platts }
301